EP20K100EFC324-1N vs EP20K30EFC324-3 Vergleich
Detaillierter Direktvergleich von EP20K100EFC324-1N von Altera und EP20K30EFC324-3 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP20K100EFC324-1N | EP20K30EFC324-3 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $108,00 | $175,00 |
| Family | APEX-20KE | APEX 20KE (MultiCore architecture) |
| Device Type | FPGA (Field Programmable Gate Array) | — |
| Logic Elements (LEs) | 4160 | — |
| Typical Gates | 100,000 | — |
| Maximum User I/O | 246 | — |
| Embedded System Blocks (ESBs) | 53248 bits | — |
| Gehäuse | 324-BGA (FineLine BGA) | 324-FBGA (19 mm x 19 mm) |
| Betriebstemperatur | 0 C to 85 C | — |
| Propagation Delay | 1.6 ns | — |
| Internal Operating Frequency | 250 MHz | — |
| Core Voltage | 1.8 V | — |
| I/O Standard Support | LVDS, SSTL, HSTL, LVTTL, LVCMOS | — |
| Process Technology | 0.15 µm all-layer copper CMOS | 1.8 V, 0.18 micrometer CMOS |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Programming Technology | SRAM-based (volatile, requires configuration device) | — |
| MultiVolt I/O | 1.8 V core with 3.3 V / 5.0 V I/O support | — |
| Series | — | APEX-20KE |
| Core Supply Voltage | — | 1.71 V to 1.89 V (1.8 V nominal) |
| Typical Gate Count | — | 30,000 gates |
| Macrocells | — | 128 |
| Total RAM Bits | — | 24,576 |
| Logic Elements (approx.) | — | 1,200 |
| User I/O | — | 120 |
| Speed Grade | — | -3 |
| Montageart | — | Surface Mount |
| Operating Temperature (max) | — | 85 C |
| MSL-Level | — | 3 |
| Peak Reflow Temperature | — | 220 C |
| LVDS I/O Support | — | Yes |
| Programming Interface | — | JTAG (in-system programmable) |
| RoHS-Status | — | unknown |