EP20K100QC240-3 vs EP20K100QC240-3V Vergleich
Detaillierter Direktvergleich von EP20K100QC240-3 von Altera und EP20K100QC240-3V von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP20K100QC240-3V - APEX 20KE FPGA 100K Gates 189 I/O 240-BFQFP | Intel
EP20K100QC240-3V ObsoleteSpezifikationsvergleich
| Parameter | EP20K100QC240-3 | EP20K100QC240-3V |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $24,50 | $87,20 |
| Manufacturer | Altera | — |
| FPGA Family | APEX-20K | — |
| Number of Logic Elements | 4160 cells | — |
| Total RAM Bits | 53248 bits | 53,248 |
| Number of User I/O | 189 | 189 |
| Typical Gate Count | 263000 gates | — |
| Core Supply Voltage | 2.5 V | — |
| Maximale Taktfrequenz | 167 MHz (family rating) | — |
| Speed Grade | -3 | -3 (fastest APEX 20KE grade) |
| Technology Process | 0.22 um | — |
| Package Type | 240-BFQFP | — |
| Anzahl der Pins | 240 | — |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperaturbereich | 0 °C to +85 °C (commercial) | — |
| Propagation Delay | [DATA_NEEDED: propagation delay timing table] | — |
| Supported I/O Standards | [DATA_NEEDED: supported I/O standards] | — |
| Configuration / JTAG Interface | [DATA_NEEDED: configuration and JTAG interface details] | — |
| RoHS Compliance | [DATA_NEEDED: RoHS compliance for non-N version] | — |
| Series | — | APEX-20KE |
| Family | — | APEX-20K |
| Logic Logic Elements / Cells | — | 4,160 |
| Total System Gates | — | 100,000 |
| Number of Logic Blocks | — | 53248 (LABs) |
| Core Voltage | — | 2.375 V to 2.625 V |
| Betriebstemperatur | — | 0C to +85C (Commercial) |
| Maximum Frequency | — | 167 MHz |
| Process Technology | — | 0.22 µm CMOS |
| Gehäuse | — | 240-BFQFP (32 x 32 mm) |
| Lead-Free / RoHS | — | Yes (-3V suffix) |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |