EP20K100QC240-3 vs EP20K160EQC240-1X Vergleich
Detaillierter Direktvergleich von EP20K100QC240-3 von Altera und EP20K160EQC240-1X von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP20K100QC240-3 | EP20K160EQC240-1X |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $24,50 | $110,00 |
| Manufacturer | Altera | — |
| FPGA Family | APEX-20K | — |
| Number of Logic Elements | 4160 cells | — |
| Total RAM Bits | 53248 bits | — |
| Number of User I/O | 189 | — |
| Typical Gate Count | 263000 gates | — |
| Core Supply Voltage | 2.5 V | — |
| Maximale Taktfrequenz | 167 MHz (family rating) | — |
| Speed Grade | -3 | -1X (slowest commercial) |
| Technology Process | 0.22 um | — |
| Package Type | 240-BFQFP | — |
| Anzahl der Pins | 240 | — |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperaturbereich | 0 °C to +85 °C (commercial) | — |
| Propagation Delay | [DATA_NEEDED: propagation delay timing table] | 1.55 ns |
| Supported I/O Standards | [DATA_NEEDED: supported I/O standards] | — |
| Configuration / JTAG Interface | [DATA_NEEDED: configuration and JTAG interface details] | — |
| RoHS Compliance | [DATA_NEEDED: RoHS compliance for non-N version] | — |
| Family | — | APEX 20KE |
| Logic Elements / Cells | — | 6,400 |
| System Gates | — | 160,000 |
| Embedded Memory (ESB) | — | [DATA_NEEDED: ESB RAM bits] |
| Maximum Internal Frequency | — | 373 MHz |
| User I/Os | — | 175 (some sources list 271 for BGA variant) |
| Core Voltage | — | 1.8 V |
| Process Technology | — | 0.22 µm CMOS |
| Gehäuse | — | 240-pin PQFP (FQFP) |
| Logic Family | — | CMOS |
| Betriebstemperatur | — | 0 °C to +85 °C |
| RoHS-Status | — | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Architecture | — | MultiCore (LUT + Embedded System Blocks) |
| Programming Interface | — | JTAG (IEEE 1149.1) |