EP20K1500CF33C8ES vs EP20K1000CF672C8ES Vergleich

Detaillierter Direktvergleich von EP20K1500CF33C8ES von Intel und EP20K1000CF672C8ES von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Intel
EP20K1500CF33C8ES EP20K1500CF33C8ES - 1.5M Gate APEX FPGA 1020-FBGA | Intel

EP20K1500CF33C8ES - 1.5M Gate APEX FPGA 1020-FBGA | Intel

EP20K1500CF33C8ES ⚠ Letzte Bestellmöglichkeit
Intel
EP20K1000CF672C8ES EP20K1000CF672C8ES - 1M-gate APEX20KE FPGA, 672-BGA | Intel

EP20K1000CF672C8ES - 1M-gate APEX20KE FPGA, 672-BGA | Intel

EP20K1000CF672C8ES ⚠ Letzte Bestellmöglichkeit

Spezifikationsvergleich

Parameter EP20K1500CF33C8ES EP20K1000CF672C8ES
Marke Intel Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Letzte Kaufgelegenheit Letzte Kaufgelegenheit
Lagerstatus In Stock In Stock
Stückpreis (USD) $288,00 $285,00
Series APEX 20K (APEX 20KE family) —
Manufacturer Intel (formerly Altera) —
System Gates 1,500,000 —
Maximum Gates (Equivalent) 2,392,000 —
Logic Elements 51,840 38,400
Embedded System Block (ESB) Bits 442,368 —
CAM Bits 216 Kbit —
Number of PLLs 4 —
Number of Clocks 8 clock pins —
Maximum User I/O 808 (1020-FBGA) —
Gehäuse 1020-FBGA (FCBGA), 33x33 mm 672-ball FineLine BGA
Montageart Surface Mount Surface Mount (BGA)
Speed Grade -1 (C8) C8
Betriebstemperatur [DATA_NEEDED: operating temperature range] Commercial (0C to +85C)
Voltage - Supply (Core) 1.8 V nominal (multiVolt I/O supports 1.8/2.5/3.3/5.0 V) —
I/O Standard Support LVTTL, LVCMOS, PCI, SSTL, HSTL, LVDS (multiVolt) —
JTAG / Boundary Scan IEEE 1149.1 compliant —
Programming Interface ByteBlaster / MasterBlaster / Altera USB-Blaster JTAG (IEEE 1149.1 / IEEE 1532)
Sample Tier ES (engineering sample) —
RoHS-Status [DATA_NEEDED: RoHS compliance for ES variant] Compliant
Lead-Free [DATA_NEEDED: lead-free status] —
Family — APEX 20K (APEX20KE)
Typical Gates — 25,920
Maximum System Gates — 1,000,000
Embedded Memory (ESB) — 216 Kbits
User I/O Pins — 508
Process Technology — 0.18 µm CMOS
Core Voltage (VCCINT) — 2.5 V
I/O Standards Supported — LVTTL, LVCMOS, PCI, LVDS, LVPECL, GTL, SSTL-2/3
PLLs — 4 (ClockLock/ClockBoost)
MSL-Level — 3 (168 hours)

Datenblätter & Ressourcen

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