EP20K160EQC240-3 vs EP20K160EQC240-2 Vergleich
Detaillierter Direktvergleich von EP20K160EQC240-3 von Intel und EP20K160EQC240-2 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP20K160EQC240-3 | EP20K160EQC240-2 |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $98,75 | $108,50 |
| Family | APEX 20K | APEX 20KE |
| Series | EP20K160E | — |
| Typical Gates | 160,000 | 160,000 |
| Maximum System Gates | 404,000 | — |
| Macrocells | 640 | — |
| Logic Elements | 4,160 | — |
| Embedded RAM Bits | 53,248 | — |
| User I/O Pins | 175 | — |
| Gehäuse | 240-pin PowerQuad Flat Pack (BQFP / FQFP) | PQFP-240 (QFP-240, FQFP) |
| Core Voltage | 1.8 V | — |
| I/O Voltage | 1.8 V / 2.5 V / 3.3 V (multi-voltage I/O banks) | — |
| Speed Grade | -3 (slowest commercial grade) | -2 |
| Process Technology | 0.18 µm CMOS | 0.18-micron SRAM CMOS |
| Betriebstemperatur | 0 °C to +85 °C (commercial) | 0 C to 85 C (Commercial) |
| JTAG Support | IEEE 1149.1 boundary-scan | IEEE Std. 1149.1 boundary-scan |
| Configuration Interface | Passive Serial, JTAG | — |
| Montageart | Surface Mount (gull-wing QFP) | Surface Mount (Gull Wing) |
| RoHS-Status | unknown | Non-compliant (original Altera-era PQFP) |
| Logic Elements (LEs) | — | 6,400 |
| Embedded System Blocks (ESBs) | — | 64 |
| Maximum Embedded Memory | — | 56 Kbits (approx. 7 Kbytes usable) |
| Maximum User I/O (this package) | — | 175 |
| Maximum User I/O (largest package) | — | 271 |
| PLLs | — | 4 |
| Internal Frequency (max) | — | 160 MHz |
| Propagation Delay | — | 1.55 ns |
| Logic Family | — | CMOS |
| Pin-Anzahl | — | 240 |
| Supply Voltage (core) | — | [DATA_NEEDED: core VCC value] |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, SSTL, GTL+, LVDS |
| Configuration Modes | — | Passive Serial, Passive Parallel Synchronous, JTAG |
| MultiCore Architecture | — | Yes (Logic + ESB + I/O) |
| 5.0 V Tolerance | — | Achievable with external resistor |