EP20K200BC356-1 vs EP20K200BC356-2XV Vergleich
Detaillierter Direktvergleich von EP20K200BC356-1 von Altera und EP20K200BC356-2XV von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP20K200BC356-2XV - APEX-20K FPGA, 8320 LE, 356-BGA | Altera/Intel
EP20K200BC356-2XV ObsoleteSpezifikationsvergleich
| Parameter | EP20K200BC356-1 | EP20K200BC356-2XV |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $335,00 | $45,00 |
| Product Function | APEX-20K Field Programmable Gate Array (FPGA) | — |
| Logic Family | CMOS | — |
| Equivalent System Gates | 200K gates | — |
| Logic Elements / Cells | 8320 | — |
| Total RAM Bits | 106496 bits | 106496 |
| Maximale Taktfrequenz | 250 MHz | — |
| Core Supply Voltage | 2.5 V | — |
| User I/O Count | 277 | — |
| Anzahl der Pins | 356 | — |
| Gehäuse / Bauform | 356-LBGA | 356-LBGA (Ball Grid Array) |
| Package Code | LBGA | — |
| Package Shape | Square | — |
| Montageart | Surface Mount | Surface Mount |
| Process Technology | 0.22 um | — |
| Propagation Delay (tPD) | 2.5 ns (from -1N variant listing) | — |
| Betriebstemperaturbereich | 0 to 85 C (commercial, per -1N variant listing) | — |
| RoHS-Status | [DATA_NEEDED: RoHS/lead finish of original non-N EP20K200BC356-1] | [DATA_NEEDED: RoHS compliance flag] |
| Lead-Free Finish | [DATA_NEEDED: original non-N finish not specified; N suffix indicates lead-free] | — |
| Family | — | APEX-20K |
| Series | — | APEX-20K® |
| Number of LABs/CLBs | — | 832 |
| Number of Logic Elements / Cells | — | 8320 |
| Number of I/O | — | 277 |
| Number of Gates | — | 526000 |
| Core Voltage Supply | — | 2.375 V to 2.625 V |
| Betriebstemperatur | — | 0 °C to 85 °C (TJ) |
| Speed Grade | — | -2 |
| Configuration Memory | — | SRAM-based (volatile) |
| Programming Interface | — | JTAG (IEEE 1149.1) |