EP20K200BC484-1X vs EP20K200EFC484-2N Vergleich
Detaillierter Direktvergleich von EP20K200BC484-1X von Altera und EP20K200EFC484-2N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP20K200BC484-1X - APEX-20K 200K-Gate FPGA 382 I/O 484-BGA | Altera
EP20K200BC484-1X ObsoleteSpezifikationsvergleich
| Parameter | EP20K200BC484-1X | EP20K200EFC484-2N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $75,10 | $175,00 |
| Product Family | APEX-20K | — |
| Series | EP20K200 | — |
| Logic Elements / Cells | 8320 | — |
| Total RAM Bits | 106496 | 106,496 |
| Number of I/O | 382 | — |
| Number of Logic Gates | 200000 | — |
| Package Type | 484-BBGA (Fine-pitch Ball Grid Array) | — |
| Package Suffix | BC484 | — |
| Speed Grade | -1 (slowest commercial grade) | -2 |
| Montageart | Surface Mount | Surface Mount (BGA) |
| Betriebstemperatur | 0C to +85C (commercial, [DATA_NEEDED: full Tjj range]) | 0 °C to +85 °C (Commercial) |
| Configuration Method | SRAM - external serial/parallel PROM | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| PLL | ClockLock / ClockBoost | — |
| Embedded Memory Blocks | Embedded System Blocks (ESBs) - RAM/ROM/CAM | — |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead-free status] |
| Family | — | APEX-20KE |
| Product Type | — | FPGA - Field Programmable Gate Array |
| System Gates | — | 200,000 |
| Logic Elements | — | 8,320 |
| Embedded System Blocks (ESB) | — | 52 (True Dual-Port RAM) |
| Maximum User I/O | — | 376 |
| Gehäuse | — | 484-FBGA (FineLine BGA), 23x23 mm, 1.0 mm pitch |
| Core Voltage | — | 1.8 V |
| Supply Voltage Range | — | 1.71 V to 1.89 V |
| Process Technology | — | 0.22 µm CMOS |
| Logic Family | — | CMOS |
| Propagation Delay (typ.) | — | 2.5 ns |
| Configuration Modes | — | Passive Serial, Passive Parallel Async, JTAG |
| PLLs | — | 4 |