EP20K200CB652C7ES vs EP20K200CF484C7ES Vergleich
Detaillierter Direktvergleich von EP20K200CB652C7ES von Altera und EP20K200CF484C7ES von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP20K200CB652C7ES - APEX 20K 200K FPGA 652-BGA | Altera/Intel
EP20K200CB652C7ES ⚠ Letzte Bestellmöglichkeit
Spezifikationsvergleich
| Parameter | EP20K200CB652C7ES | EP20K200CF484C7ES |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $275,00 | $92,00 |
| Family | APEX 20K | APEX-20KC |
| Logic Elements | 8,320 | — |
| Embedded System Block (ESB) RAM | 106,496 bits | — |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O count for 652-BGA] | — |
| Core Voltage (VCCINT) | 1.8 V | — |
| I/O Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| Speed Grade | -7 | C7 (7 ns) |
| Operating Temperature (Commercial) | 0 °C to +85 °C | — |
| Gehäuse | 652-BGA | — |
| Montageart | Surface Mount | Surface Mount |
| Configuration Method | SRAM (volatile, requires external PROM on power-up) | — |
| PLL Count | Up to 8 | — |
| Supported I/O Standards | LVTTL, LVCMOS, PCI, GTL+, SSTL, LVDS | — |
| JTAG (IEEE 1149.1) | Yes (boundary-scan) | — |
| Configuration Device Compatibility | EPC2, EPC8, EPC16, EPC64, microprocessor | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: rohs_status] |
| MSL-Level | [DATA_NEEDED: moisture sensitivity level] | — |
| Series | — | APEX 20KC |
| Logic Elements / Cells | — | 8,320 |
| Typical Gates | — | 200,000 |
| Number of LABs/CLBs | — | 376 |
| Total RAM Bits | — | 106,496 |
| Number of I/O | — | 377 (max) |
| Voltage - Supply | — | 1.8 V core |
| Betriebstemperatur | — | 0C to +85C (commercial) |
| Gehäuse / Bauform | — | 484-BBGA (FineLine BGA) |
| Process Technology | — | 0.18 µm CMOS |
| Silicon Status | — | ES (Engineering Sample) |
| Maximum Internal Frequency | — | 375.94 MHz |
| Number of PLLs | — | [DATA_NEEDED: pll_count] |