EP20K200CF484C8ES vs EP20K200CF484C7N Vergleich
Detaillierter Direktvergleich von EP20K200CF484C8ES von Altera und EP20K200CF484C7N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP20K200CF484C8ES - APEX-20KC 200K Gates FPGA | Altera
EP20K200CF484C8ES ⚠ Letzte BestellmöglichkeitAltera
EP20K200CF484C7N - APEX-20K 200K Gates FPGA 484-FBGA | Intel/Altera
EP20K200CF484C7N ObsoleteSpezifikationsvergleich
| Parameter | EP20K200CF484C8ES | EP20K200CF484C7N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $89,00 | $62,00 |
| Series | APEX-20KC | APEX-20K |
| Family | APEX 20K | — |
| Logic Elements | 8,320 | — |
| System Gates | 200,000 | — |
| Embedded Memory (RAM bits) | 106,496 | — |
| Number of Logic Array Blocks (LABs) | 104 | — |
| Number of Embedded System Blocks (ESBs) | 13 | — |
| User I/O Pins (max) | 376 | — |
| PLLs | 4 | — |
| Core Voltage | 1.8 V | — |
| Speed Grade | C8 (-8 commercial) | — |
| Gehäuse | 484-pin FBGA (FineLine BGA) | — |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | 0C to +85C (commercial) | 0C to +85C (commercial grade) |
| Process Node | 0.18 micron CMOS | — |
| Configuration Interface | JTAG (IEEE 1149.1) / Altera serial | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL, SSTL, HSTL, AGP | — |
| Lead Free / RoHS | [DATA_NEEDED: lead-free status] | — |
| Logic Elements / Cells | — | 8,320 |
| Total RAM Bits | — | 106,496 |
| Number of Gates (typical) | — | 200,000 |
| Number of I/O | — | 382 |
| Voltage - Supply (VCCINT) | — | 1.71 V to 1.89 V |
| Gehäuse / Bauform | — | 484-BBGA (FineLine BGA) |
| Supplier Device Package | — | 484-FBGA (23x23 mm) |
| Number of PLLs | — | 4 |
| Embedded Array Blocks (EABs) | — | Configurable as RAM/ROM/FIFO |
| Programmable Logic Blocks | — | APEX LAB architecture |
| MultiVolt I/O Support | — | 1.8V / 2.5V / 3.3V / 5V |
| Configuration Method | — | SRAM-based, in-system reconfigurable |
| RoHS-Status | — | [DATA_NEEDED: RoHS compliance status] |
| Lebenszyklusstatus | — | Obsolete (Altera/Intel APEX-20K family EOL) |