EP20K200CF484C8ES vs EP20K200EQC208-3 Vergleich
Detaillierter Direktvergleich von EP20K200CF484C8ES von Altera und EP20K200EQC208-3 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP20K200CF484C8ES - APEX-20KC 200K Gates FPGA | Altera
EP20K200CF484C8ES ⚠ Letzte Bestellmöglichkeit
Spezifikationsvergleich
| Parameter | EP20K200CF484C8ES | EP20K200EQC208-3 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $89,00 | $65,00 |
| Series | APEX-20KC | APEX 20K (enhanced "E" variant) |
| Family | APEX 20K | APEX 20KE |
| Logic Elements | 8,320 | — |
| System Gates | 200,000 | — |
| Embedded Memory (RAM bits) | 106,496 | — |
| Number of Logic Array Blocks (LABs) | 104 | — |
| Number of Embedded System Blocks (ESBs) | 13 | — |
| User I/O Pins (max) | 376 | — |
| PLLs | 4 | — |
| Core Voltage | 1.8 V | — |
| Speed Grade | C8 (-8 commercial) | -3 |
| Gehäuse | 484-pin FBGA (FineLine BGA) | 208-BFQFP / PQFP208 (Plastic Quad Flat Pack, gull-wing) |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | 0C to +85C (commercial) | — |
| Process Node | 0.18 micron CMOS | — |
| Configuration Interface | JTAG (IEEE 1149.1) / Altera serial | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL, SSTL, HSTL, AGP | — |
| Lead Free / RoHS | [DATA_NEEDED: lead-free status] | — |
| Product Type | — | FPGA (Field Programmable Gate Array), SRAM-based, in-system programmable |
| System Gates (typical) | — | 200,000 |
| Logic Elements (LEs) | — | 8,320 |
| Embedded RAM Bits | — | 106,496 |
| Maximum User I/O | — | 136 |
| Core Supply Voltage (VCCINT) | — | 2.5 V (typical, APEX 20KE generation) |
| I/O Supply Voltage (VCCIO) | — | MultiVolt, 1.8 V / 2.5 V / 3.3 V / 5 V compatible |
| Terminal Pitch | — | 0.5 mm |
| Technology | — | CMOS, SRAM configuration cell |
| Configuration Mode | — | Fast Passive Parallel (FPP), Passive Serial (PS), JTAG (IEEE 1149.1) |
| Embedded Array Blocks (EABs) | — | Yes (dual-port RAM/ROM, up to 16-bit wide) |
| MultiVolt I/O Support | — | Yes |
| LVDS Support | — | True-LVDS (enhanced "E" variant feature) |
| Feuchtigkeitsempfindlichkeitsgrad (MSL) | — | 3 (168 Hours) |
| RoHS-Status | — | [DATA_NEEDED: RoHS compliance status] |
| Operating Temperature (Commercial) | — | 0 °C to 85 °C |