EP20K200EFC484-1 vs EP20K200EFC484-2X Vergleich
Detaillierter Direktvergleich von EP20K200EFC484-1 von Altera und EP20K200EFC484-2X von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP20K200EFC484-1 - APEX 20KE FPGA 200K Gates 484-BGA | Altera
EP20K200EFC484-1 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP20K200EFC484-1 | EP20K200EFC484-2X |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $68,40 | $54,40 |
| Family | APEX 20KE | APEX-20KE |
| Logic Elements / Cells | 8320 | — |
| System Gates | 200000 | — |
| Embedded Memory (Bits) | 106496 | — |
| Maximum User I/O | 376 | — |
| Number of PLLs | 4 | — |
| Core Voltage | 1.8 V | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Gehäuse | 484-BGA (FineLine BGA) | 484-FBGA (23x23 mm) |
| Package Ball Count | 484 | — |
| Montageart | Surface Mount | — |
| Betriebstemperatur | -40 °C to +85 °C (industrial, inferred from grade code) | 0 °C to 85 °C |
| I/O Standard Support | LVDS, PCI, LVTTL, LVCMOS, SSTL, HSTL | — |
| Programming Interface | IEEE 1149.1 JTAG, passive serial, passive parallel | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance] |
| MSL-Level | [DATA_NEEDED: MSL moisture sensitivity level] | — |
| Logic Elements | — | 8,320 |
| LABs/CLBs | — | 832 |
| Total RAM Bits | — | 106,496 |
| Gate Count | — | 200,000 |
| User I/O Pins | — | 376 |
| Max Operating Frequency | — | 205 MHz |
| Core Supply Voltage (VCCINT) | — | 1.71 V to 1.89 V (1.8 V nominal) |
| I/O Supply Voltage (VCCIO) | — | 3.3 V / 2.5 V (multi-standard) |
| Package Code | — | BGA, Ball, Square |
| Propagation Delay | — | 2.5 ns |
| Speed Grade | — | -2X |