EP20K200EFC484-1 vs EP20K200EFI484-2X Vergleich
Detaillierter Direktvergleich von EP20K200EFC484-1 von Altera und EP20K200EFI484-2X von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP20K200EFC484-1 - APEX 20KE FPGA 200K Gates 484-BGA | Altera
EP20K200EFC484-1 ⚠ Letzte Bestellmöglichkeit
Spezifikationsvergleich
| Parameter | EP20K200EFC484-1 | EP20K200EFI484-2X |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $68,40 | $215,00 |
| Family | APEX 20KE | APEX 20KE |
| Logic Elements / Cells | 8320 | — |
| System Gates | 200000 | 200,000 |
| Embedded Memory (Bits) | 106496 | — |
| Maximum User I/O | 376 | — |
| Number of PLLs | 4 | — |
| Core Voltage | 1.8 V | 1.8 V |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Gehäuse | 484-BGA (FineLine BGA) | 484-ball FineLine BGA |
| Package Ball Count | 484 | — |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | -40 °C to +85 °C (industrial, inferred from grade code) | -40 °C to +100 °C (TJ) |
| I/O Standard Support | LVDS, PCI, LVTTL, LVCMOS, SSTL, HSTL | — |
| Programming Interface | IEEE 1149.1 JTAG, passive serial, passive parallel | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | — |
| MSL-Level | [DATA_NEEDED: MSL moisture sensitivity level] | — |
| Series | — | EP20K200E |
| Logic Elements | — | 8,320 |
| Embedded RAM Bits | — | 106,496 |
| User I/O Pins | — | 376 |
| Maximum Frequency | — | 205 MHz |
| Propagation Delay | — | 1.97 ns |
| Architecture | — | MultiCore (LUT + Embedded System Blocks) |
| Configuration Interface | — | JTAG (IEEE 1149.1) + Serial/Parallel PROM |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, GTL+ (per APEX 20KE family datasheet) |