EP20K200EFC484-1N vs EP20K200FC484-1N Vergleich
Detaillierter Direktvergleich von EP20K200EFC484-1N von Altera und EP20K200FC484-1N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP20K200EFC484-1N | EP20K200FC484-1N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $290,00 | $118,00 |
| Family | APEX-20KE | APEX 20K |
| Logic Elements | 8,320 | — |
| System Gates | 200,000 | 200,000 (approx.) |
| Embedded RAM Bits | 106,496 | — |
| Maximum User I/O | 376 | 382 |
| Core Voltage (VCCINT) | 1.8 V (1.71 V to 1.89 V) | — |
| I/O Voltage (VCCIO) | [DATA_NEEDED: VCCIO range] | — |
| Maximum Internal Frequency | 367 MHz | 250 MHz |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Propagation Delay | 2.5 ns (per digchip reference) | 2.5 ns |
| Gehäuse | 484-ball FineLine BGA (23 mm × 23 mm) | 484-FBGA (23 x 23 mm) |
| Betriebstemperatur | 0 °C to +85 °C (commercial) | 0 °C to +85 °C |
| Speed Grade | -1 | — |
| Programming Interface | IEEE 1149.1 JTAG | — |
| Montageart | Surface Mount (BGA) | Surface Mount |
| MSL-Level | [DATA_NEEDED: MSL rating] | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | — |
| Series | — | APEX-20K® |
| Logic Elements / Cells | — | 8,320 |
| Number of Macros | — | 832 |
| Supply Voltage (Core) | — | 2.5 V (2.375 V – 2.625 V) |
| Package Code | — | BGA / FBGA |
| Number of Pins/balls | — | 484 |
| Lead-Free / RoHS | — | Compliant (per distributor listings) |
| Architecture | — | MultiCore (LUT + product-term + embedded memory) |
| Configuration Method | — | SRAM-based, JTAG/ByteBlaster |