EP20K30EFC144-3 vs EP20K30EFC144-2X Vergleich

Detaillierter Direktvergleich von EP20K30EFC144-3 von Altera und EP20K30EFC144-2X von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Altera
EP20K30EFC144-2X EP20K30EFC144-2X - 30K Gate APEX 20K FPGA | Altera

EP20K30EFC144-2X - 30K Gate APEX 20K FPGA | Altera

EP20K30EFC144-2X Obsolete

Spezifikationsvergleich

Parameter EP20K30EFC144-3 EP20K30EFC144-2X
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $10,40 $58,50
Series APEX-20K —
Family APEX-20K FPGA —
Logic Elements / Cells 1200 —
Total System Gates 30,000 (typical) —
Total RAM Bits 24576 —
Number of User I/Os (per pkg) 92 (144-LQFP) —
User I/Os (max per family) 408 —
Internal Operating Frequency 160 MHz —
Propagation Delay 1.68 ns (typical) —
Logic Family CMOS —
Process Technology 0.22 um 0.22 um
Core Supply Voltage 1.71 V to 1.89 V 1.8 V
Architecture MultiCore (LUT + product-term + ESB) —
Gehäuse / Bauform 144-LQFP (20x20 mm) —
Montageart Surface Mount Surface Mount
Betriebstemperatur 0C to +85C —
Speed Grade -3 -2X
RoHS-Status [DATA_NEEDED: RoHS status] unknown
Development Tool (legacy) Quartus II / MAX+PLUS II —
Device Family — Altera APEX 20K
Device Type — Loadable programmable logic device (FPGA/CPLD hybrid)
Typical Gates — 30,000 gates
Number of Logic Elements / Cells — 1,200 cells (third-party parametric listing)
Number of Macrocells — 192
Number of User I/O — 93
Number of Terminals — 144
Terminal Form — Ball
Package Code — LBGA / 144-FBGA
Package Shape — Square
Betriebstemperaturbereich — [DATA_NEEDED: exact operating temperature range]
Embedded RAM Bits — [DATA_NEEDED: embedded memory size]
Supported I/O Standards — [DATA_NEEDED: supported I/O standards]
Configuration Schemes — [DATA_NEEDED: supported configuration schemes]

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