EP20K400BC652-2AA vs EP20K400FC784-2 Vergleich
Detaillierter Direktvergleich von EP20K400BC652-2AA von Intel und EP20K400FC784-2 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP20K400BC652-2AA | EP20K400FC784-2 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $175,00 |
| Product Type | Field-programmable gate array (FPGA) | — |
| Series | APEX-20K | — |
| Number of LABs/CLBs | 1664 | — |
| Number of Logic Elements/Cells | 16640 | — |
| Total RAM Bits | 212992 bit | — |
| Number of I/O | 502 | — |
| Number of Gates | 1052000 | — |
| Versorgungsspannung | 2.375 V to 2.625 V | — |
| Montageart | Surface Mount | Surface Mount (BGA) |
| Betriebstemperatur | 0 °C to 85 °C (TJ) | [DATA_NEEDED: exact Tj range] |
| Gehäuse | 652-BGA | 784-Ball FineLine BGA (FC) |
| Supplier Device Package | 652-BGA (45x45) [DATA_NEEDED: target-device package dimensions] | — |
| Part Status | Obsolete | — |
| Configuration Memory Technology | [DATA_NEEDED: configuration memory technology] | — |
| Maximum User I/O Frequency | [DATA_NEEDED: maximum user I/O frequency] | — |
| Core Logic Voltage | [DATA_NEEDED: core logic voltage] | — |
| Typical Supply Current | [DATA_NEEDED: typical supply current] | — |
| RoHS-Status | unknown | [DATA_NEEDED: not confirmed in provided data] |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | unknown | — |
| Family | — | APEX 20K |
| Device Family Member | — | EP20K400C |
| Typical System Gates | — | 400,000 |
| Maximum User I/O Pins | — | 488 (784-BGA) |
| Logic Elements | — | 16,640 |
| Embedded RAM (ESB) | — | 212 Kbits |
| Maximum Block RAM | — | [DATA_NEEDED: block RAM organization per ESB] |
| Maximum Frequency (internal) | — | [DATA_NEEDED: fmax, datasheet-dependent] |
| Process Technology | — | 0.22 µm CMOS SRAM |
| Core Voltage | — | 2.5 V |
| MultiVolt I/O Voltage | — | 1.8 V / 2.5 V / 3.3 V |
| Supported I/O Standards | — | LVTTL, LVCMOS, PCI, SSTL-2, SSTL-3, GTL+, CTT |
| Configuration Mode | — | Serial / Parallel SRAM-volatile (external PROM required) |
| Speed Grade | — | -2 (industrial) |
| MSL-Level | — | 3 (per Partstack listing) |
| Peak Reflow Temperature | — | 220 °C (per Partstack listing) |
| Hot Socketing | — | Supported |
| JTAG / Boundary-Scan | — | IEEE 1149.1 compliant |