EP20K400CB652C7ES vs EP20K400CB652I7 Vergleich
Detaillierter Direktvergleich von EP20K400CB652C7ES von Altera und EP20K400CB652I7 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP20K400CB652C7ES | EP20K400CB652I7 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $215,00 | $149,50 |
| Series | APEX 20KC | — |
| Family | FPGA APEX 20KC | APEX 20KC |
| System Gates | 400,000 | — |
| Logic Cells | 16,640 | — |
| Number of Inputs | 488 | — |
| Number of I/O Lines | 484 | — |
| Anzahl der Ausgänge | 484 | — |
| Propagation Delay | 1.4 ns | — |
| Maximale Taktfrequenz | 1666.6 MHz | — |
| Internal Performance | 375.94 MHz | — |
| Process Technology | 0.15 µm | 0.15 µm CMOS |
| Core Supply Voltage | 1.8 V | 1.8 V |
| Package Type | BGA (S-PBGA-B652) | — |
| Number of Terminals | 652 | — |
| Package Body Material | Plastic / Epoxy | — |
| Surface Mount | Yes | — |
| Speed Grade | C7 | 7 |
| Betriebstemperatur | [DATA_NEEDED: Operating temperature] | — |
| RoHS-Status | [DATA_NEEDED: RoHS] | Non-compliant (JESD-609 e0, contains lead) |
| Device Family | — | Field-Programmable Gate Array (FPGA) |
| Typical Gates | — | 400,000 |
| Logic Elements (LEs) | — | 16,640 |
| Maximum Operating Frequency | — | 375.94 MHz |
| I/O Supply Voltage | — | 1.8 V / 3.3 V |
| Gehäuse | — | BGA-652 (652-ball) |
| Package Code (JESD-30) | — | S-PBGA-B652 |
| Terminal Form | — | Ball |
| Package Shape | — | Square |
| Maximum User I/O Pins | — | [DATA_NEEDED: max user I/O] |
| Embedded Memory | — | Embedded System Blocks (ESB) - dual-port RAM / FIFO / CAM |
| Configuration Method | — | SRAM + JTAG (ISP) |
| Temperature Grade | — | Industrial (-40 °C to +100 °C) |
| Manufacturer Status | — | Obsolete (Intel/Altera legacy FPGA) |