EP20K400CB652I8N vs EP20K400CB652I7 Vergleich
Detaillierter Direktvergleich von EP20K400CB652I8N von Altera und EP20K400CB652I7 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP20K400CB652I8N | EP20K400CB652I7 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $115,00 | $149,50 |
| Family | APEX 20KC | APEX 20KC |
| Logic Elements | 16,640 | — |
| System Gates | 400,000 | — |
| Macrocells | 1664 | — |
| Number of User I/O | 488 | — |
| Number of Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | — |
| Number of Embedded System Blocks (ESBs) | [DATA_NEEDED: ESB count] | — |
| Number of PLLs | 4 | — |
| Embedded Memory (Max) | [DATA_NEEDED: total embedded memory bits] | — |
| Maximum Operating Frequency | 301.21 MHz | 375.94 MHz |
| Process Technology | 0.15 µm CMOS | 0.15 µm CMOS |
| Core Voltage | 1.8 V | — |
| I/O Voltage (MultiVolt) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Operating Temperature (Industrial) | -40°C to +100°C | — |
| Speed Grade | 8 | 7 |
| Gehäuse | 652-pin BGA | BGA-652 (652-ball) |
| Montageart | Surface Mount | — |
| Configuration Interface | JTAG / Passive Serial | — |
| RoHS-Status | unknown | Non-compliant (JESD-609 e0, contains lead) |
| Lead-Free | unknown | — |
| Design Tool | Altera Quartus II (APEX 20KC support) | — |
| Device Family | — | Field-Programmable Gate Array (FPGA) |
| Typical Gates | — | 400,000 |
| Logic Elements (LEs) | — | 16,640 |
| Core Supply Voltage | — | 1.8 V |
| I/O Supply Voltage | — | 1.8 V / 3.3 V |
| Package Code (JESD-30) | — | S-PBGA-B652 |
| Terminal Form | — | Ball |
| Package Shape | — | Square |
| Maximum User I/O Pins | — | [DATA_NEEDED: max user I/O] |
| Embedded Memory | — | Embedded System Blocks (ESB) - dual-port RAM / FIFO / CAM |
| Configuration Method | — | SRAM + JTAG (ISP) |
| Temperature Grade | — | Industrial (-40 °C to +100 °C) |
| Manufacturer Status | — | Obsolete (Intel/Altera legacy FPGA) |