EP20K400CF672C7 vs EP20K400CB652C9N Vergleich
Detaillierter Direktvergleich von EP20K400CF672C7 von Altera und EP20K400CB652C9N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP20K400CF672C7 | EP20K400CB652C9N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $195,00 | $195,00 |
| Series | APEX-20KC | EP20K400 |
| Family | APEX 20KC (MultiCore™) | APEX 20KC |
| Logic Elements / Cells | 16,640 | — |
| System Gates | 400,000 | 400,000 |
| Embedded Memory (RAM bits) | 212,992 | — |
| Maximum User I/O | 488 | — |
| Number of I/O Banks | 8 | — |
| Gehäuse | 672-BBGA (FC-FBGA, FineLine BGA) | BGA-652 (Plastic Ball Grid Array, 652 balls) |
| Pin-Anzahl | 672 | — |
| Core Voltage | 1.8 V | — |
| Versorgungsspannung | 2.5 V (I/O reference) | — |
| Process Technology | 0.15 µm CMOS | — |
| Propagation Delay (tPD) | 2.5 ns | — |
| Maximum Internal Frequency | 375.94 MHz | 250 MHz |
| Betriebstemperatur | 0 °C to +85 °C (Commercial, C-grade) | — |
| PLL Count | 4 | — |
| Speed Grade | -7 | — |
| Montageart | Surface Mount (BGA) | Surface Mount |
| RoHS-Status | Non-compliant (legacy product) | Unknown (legacy Altera part - verify with distributor) |
| Lead-Free | Contains lead (legacy BGA finish) | — |
| Device Type | — | Programmable Logic Device (SOPC FPGA) |
| Architecture | — | MultiCore (LUT logic + Embedded System Blocks) |
| Logic Elements | — | 16,640 |
| Maximum User I/Os | — | 502 |
| Total Memory Bits | — | 212,992 (per chip) |
| Propagation Delay | — | 2.0 ns |
| Logic Family | — | CMOS |
| Core Process Technology | — | 0.15 µm all-layer copper CMOS |
| Core Supply Voltage (VCCINT) | — | 1.8 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V |
| Betriebstemperaturbereich | — | 0 °C to +85 °C (Commercial) |
| Configuration Interface | — | IEEE 1149.1 JTAG, serial passive parallel async |