EP20K400CF672C7ES vs EP20K400CF672C-8 Vergleich
Detaillierter Direktvergleich von EP20K400CF672C7ES von Altera und EP20K400CF672C-8 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP20K400CF672C7ES | EP20K400CF672C-8 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $152,00 | $95,00 |
| Family | APEX 20KC | APEX 20K |
| Series | EP20K400 | — |
| Device Type | Loadable PLD / FPGA | — |
| Logic Elements (Cells) | 16,640 | — |
| System Gates | 400,000 | — |
| Embedded Memory (Bits) | 212,992 | — |
| Total RAM Bits | 212,992 | — |
| Maximum User I/O | 488 | 488 |
| I/O Lines | 484 | — |
| Input Lines | 488 | — |
| Number of PLLs | 4 | — |
| Maximum Internal Clock Frequency | 375.94 MHz | — |
| Propagation Delay | 1.4 ns | — |
| Process Technology | 0.18 um CMOS | 0.15 µm all-layer copper CMOS |
| Core Voltage | 1.8 V | — |
| MultiVolt I/O | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Speed Grade | C7 (commercial, -7) | -8 |
| Betriebstemperatur | 0C to +85C (commercial) | — |
| Package Type | 672-ball FineLine BGA | PBGA-672 (FineLine BGA, 27 x 27 mm, 1.0 mm pitch) |
| Package Code | FC-FBGA-B672 | — |
| Ball Pitch | 1.000 mm | — |
| Montageart | Surface Mount | Surface Mount (BGA) |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Logic Elements | — | 16,640 |
| Typical Gates | — | 400,000 |
| Macros | — | 1,664 |
| Number of I/O Banks | — | [DATA_NEEDED: number of I/O banks] |
| Core Voltage (VCCINT) | — | 1.8 V nominal (1.71 V to 1.89 V) |
| I/O Voltage (VCCIO) | — | [DATA_NEEDED: VCCIO options] |
| Pin-to-Pin Delay (tPD) | — | 1.78 ns (speed grade -8) |
| Temperature Grade (C) | — | Commercial, 0 °C to 85 °C |
| Embedded Memory Type | — | ESB (RAM / ROM / CAM) |
| Configuration Interface | — | JTAG (IEEE 1149.1), Passive Serial, Passive Parallel |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |
| MSL-Level | — | [DATA_NEEDED: MSL level] |