EP20K400EBC652-1X vs EP20K400GC655-1 Vergleich
Detaillierter Direktvergleich von EP20K400EBC652-1X von Intel und EP20K400GC655-1 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 ObsoleteSpezifikationsvergleich
| Parameter | EP20K400EBC652-1X | EP20K400GC655-1 |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $92,00 | $135,00 |
| Family | APEX 20KE | APEX 20K |
| Series | APEX-20KE® | EP20K400 |
| Logic Elements / Cells | 16640 | — |
| System Gates | 1052000 (typical marketing) | — |
| Embedded Memory (bits) | 212992 | — |
| Number of Macrocells | 1664 | — |
| Number of User I/Os | 488 | — |
| Supply Voltage - Core | 1.8 V (1.71 V to 1.89 V) | — |
| Supply Voltage - I/O | 2.5 V (multi-voltage I/O supported) | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Gehäuse / Bauform | 652-BGA (45 x 45 mm) | — |
| Supplier Device Package | 652-BGA | — |
| Betriebstemperatur | 0 °C to +85 °C (Commercial) | 0 °C to +85 °C (commercial) |
| Speed Grade | -1X (faster bin) | — |
| Montageart | Surface Mount | Through-Hole |
| Propagation Delay (per macrocell) | [DATA_NEEDED: per-datasheet ns] | — |
| RoHS-Status | [DATA_NEEDED: not confirmed for this specific lot] | Non-compliant (contains lead in ceramic package) |
| Lead-Free | Yes (per modern distribution) | — |
| Logic Elements | — | 16,640 |
| Maximum Gates | — | 1,052,000 |
| Typical Gates | — | 400,000 |
| Embedded System Blocks (ESBs) | — | 4 |
| Total RAM Bits | — | 212,992 |
| Maximum User I/O | — | 502 |
| Dedicated Inputs | — | 6 |
| Core Supply Voltage | — | 2.5 V |
| I/O Supply Voltage | — | 3.3 V |
| Maximum Internal Frequency | — | 250 MHz |
| Propagation Delay | — | 2.5 ns |
| Gehäuse | — | 655-pin CPGA (Ceramic Pin Grid Array) |
| Pin-Anzahl | — | 655 |
| Configuration Modes | — | Passive Serial, Passive Parallel Async, Passive Parallel Sync |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |