EP20K400FI672-2 vs EP20K400FI672-3 Vergleich
Detaillierter Direktvergleich von EP20K400FI672-2 von Altera und EP20K400FI672-3 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP20K400FI672-2 - 400K Gates APEX-20K FPGA, 502 I/O, 672-FBGA | Altera
EP20K400FI672-2 ObsoleteSpezifikationsvergleich
| Parameter | EP20K400FI672-2 | EP20K400FI672-3 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $92,40 | $195,00 |
| Family | APEX-20K | APEX 20K |
| Logic Elements | 16640 | 16640 |
| Maximum Gates | 400,000 gates | — |
| User I/Os | 502 | — |
| Embedded Memory Bits | 212992 | — |
| Number of Macros | 1664 | — |
| Process Technology | 0.22 µm CMOS | CMOS |
| Core Supply Voltage | 2.5 V | — |
| Maximum Internal Frequency | 200 MHz | — |
| Propagation Delay | 2.5 ns | 3.6 ns |
| Betriebstemperatur | 0 °C to +85 °C (Commercial) | [DATA_NEEDED: operating temperature range] |
| Package Type | 672-pin Fine-pitch Ball Grid Array (FBGA/FCBGA) | PBGA (Plastic BGA) |
| PLLs (Phase-Locked Loops) | 4 | — |
| Configuration Modes | JTAG, Passive Serial, Passive Parallel | — |
| RoHS-Status | Lead-free / RoHS Compliant | — |
| Montageart | Surface Mount (BGA) | Surface Mount |
| Series | — | EP20K400 |
| Total Gates | — | up to 400000 |
| Embedded RAM | — | 212992 bits |
| Maximum User I/O | — | 502 |
| Dedicated Inputs | — | 6 |
| Maximale Taktfrequenz | — | 833 MHz |
| Supply Voltage (Nominal) | — | 2.5 V |
| Supply Voltage Range | — | 2.375 V to 2.625 V |
| Package Code | — | S-PBGA-B672 |
| Terminal Count | — | 672 |
| Terminal Pitch | — | 1.000 mm |
| Package Shape | — | Square BGA |
| Configuration Interface | — | JTAG (IEEE 1149.1) |
| MSL-Level | — | 3 |
| Peak Reflow Temperature | — | 220 C |