EP20K400GC655-2V vs EP20K400GC655-3V Vergleich
Detaillierter Direktvergleich von EP20K400GC655-2V von Altera und EP20K400GC655-3V von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP20K400GC655-2V - 400K Gate APEX-20KC FPGA 655-CPGA | Altera
EP20K400GC655-2V ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP20K400GC655-2V | EP20K400GC655-3V |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $92,75 | $160,00 |
| Series | APEX-20KC | APEX-20KC |
| Family | APEX 20KC (1.8 V, LVDS) | APEX 20KC (Apex 20KE Device Family, 1.8 V, LVDS) |
| Logic Elements | 16,640 | 16640 |
| Total RAM Bits | 212,992 | 212992 |
| System Gates | ~400,000 (typical marketing figure) | — |
| Number of I/O | [DATA_NEEDED: I/O count] | — |
| Core Voltage (VCCINT) | 2.375 V to 2.625 V (nominal 2.5 V) | — |
| Propagation Delay | 3.000 ns | 3.6 ns |
| Process Technology | CMOS, 0.18 um | CMOS |
| LVDS Support | Yes | — |
| Gehäuse | 655-CPGA (62.48 x 62.48 mm) | 655-BCPGA (62.48 mm x 62.48 mm) |
| Package Type | Ceramic Pin Grid Array, through-hole | — |
| Montageart | Through-hole (CPGA) | Through Hole (CPGA) |
| Speed Grade | -2 | -3V (commercial temperature, Vcc 1.8 V) |
| Betriebstemperatur | [DATA_NEEDED: temperature grade] | [DATA_NEEDED: commercial / industrial / military grade] |
| RoHS-Status | unknown | [DATA_NEEDED: RoHS compliance flag - BCPGA package often non-RoHS] |
| Lead-Free | unknown | — |
| Architecture | MultiCore (LUT + product-term + embedded memory) | — |
| Manufacturer | — | Altera (now Intel) |
| Core Supply Voltage | — | 1.71 V to 1.89 V (1.8 V nominal) |
| Typical Gate Count | — | 400000 |
| Number of User I/O | — | 496 |
| Maximale Taktfrequenz | — | 714.2 MHz |
| Package Equivalence Code | — | SPGA655, 47x47 |
| Peak Reflow Temperature | — | 220 C |
| Configuration | — | SRAM-based (requires EPC configuration device) |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |