EP20K400GC655-3X vs EP20K400GC655-3 Vergleich

Detaillierter Direktvergleich von EP20K400GC655-3X von Altera und EP20K400GC655-3 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Intel
EP20K400GC655-3 EP20K400GC655-3 - 400K Gate APEX-20KC FPGA 655-BCPGA | Intel

EP20K400GC655-3 - 400K Gate APEX-20KC FPGA 655-BCPGA | Intel

EP20K400GC655-3 ⚠ Letzte Bestellmöglichkeit

Spezifikationsvergleich

Parameter EP20K400GC655-3X EP20K400GC655-3
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Letzte Kaufgelegenheit
Lagerstatus In Stock In Stock
Stückpreis (USD) $65,00 $310,00
Series APEX-20KC APEX-20KC
Family APEX 20K (MultiCore architecture, LUT + product-term + embedded memory) APEX 20K
Manufacturer Altera (now Intel FPGA) Intel (formerly Altera)
Logic Elements / Cells 16,640 —
System Gates 400,000 —
Total RAM Bits 212,992 bits 212992
Maximum Internal Frequency 167 MHz (speed grade -3) —
Process Technology 0.22 µm CMOS 0.22 um CMOS
Core Supply Voltage (VCCINT) 1.71 V to 1.89 V —
I/O Supply Voltage (VCCIO) 2.5 V (LVDS support per APEX 20KE datasheet) —
Gehäuse / Bauform 655-BCPGA (CPGA655, 62.48 x 62.48 mm) 655-BCPGA
Montageart Through-Hole (CPGA, ceramic) —
Betriebstemperatur [DATA_NEEDED: operating temperature range] -40C to +85C (industrial)
Speed Grade -3 (fastest) -3 (slowest grade in family)
Suffix Code -X (extended / ceramic CPGA variant) —
I/O Count [DATA_NEEDED: max user I/O] —
JTAG / Boundary Scan IEEE 1149.1 (per APEX 20K family) —
RoHS-Status [DATA_NEEDED: RoHS status - ceramic CPGA historically non-RoHS] [DATA_NEEDED: rohs status]
Logic Elements — 16640
Number of Gates — 400000
Supply Voltage - Core — 1.71 V to 1.89 V (1.8 V nominal)
I/O Voltage Tolerance — MultiVolt I/O: 1.8 V / 2.5 V / 3.3 V / 5 V
Maximum Frequency — 167 MHz (per FPGAkey)
Supplier Device Package — 655-CPGA (62.48 x 62.48 mm)
Propagation Delay (tPD) — 3.6 ns (per Microchip USA listing)
JTAG Support — IEEE 1149.1 Boundary-Scan
Configuration Modes — Passive Serial, Passive Parallel Sync/Async, Active Serial

Datenblätter & Ressourcen

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