EP20K400GI655-1 vs EP20K400GC655-1 Vergleich
Detaillierter Direktvergleich von EP20K400GI655-1 von Altera und EP20K400GC655-1 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 ObsoleteSpezifikationsvergleich
| Parameter | EP20K400GI655-1 | EP20K400GC655-1 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $195,00 | $135,00 |
| Family | APEX 20K | APEX 20K |
| Device Series | EP20K400 | — |
| Technology | CMOS, SRAM-based | — |
| Logic Elements | 16640 | 16,640 |
| Typical Gates | 400000 | 400,000 |
| Maximum User I/O | 502 | 502 |
| Dedicated Inputs | 4 | 6 |
| Total Terminals | 655 | — |
| Propagation Delay | 2.5 ns | 2.5 ns |
| Package Type | Ceramic Pin Grid Array (CPGA-655) | — |
| JESD-30 Package Code | S-CPGA-P655 | — |
| Betriebstemperatur | -40C to +85C (Industrial) | 0 °C to +85 °C (commercial) |
| Moisture Sensitivity Level | MSL 1 | — |
| Peak Reflow Temperature | 220 C | — |
| Programmability | In-system, JTAG boundary-scan (IEEE 1149.1) | — |
| Process Node | 0.18 micrometer CMOS | — |
| RoHS-Status | Compliant | Non-compliant (contains lead in ceramic package) |
| Series | — | EP20K400 |
| Maximum Gates | — | 1,052,000 |
| Embedded System Blocks (ESBs) | — | 4 |
| Total RAM Bits | — | 212,992 |
| Process Technology | — | 0.22 µm CMOS |
| Core Supply Voltage | — | 2.5 V |
| I/O Supply Voltage | — | 3.3 V |
| Maximum Internal Frequency | — | 250 MHz |
| Gehäuse | — | 655-pin CPGA (Ceramic Pin Grid Array) |
| Pin-Anzahl | — | 655 |
| Montageart | — | Through-Hole |
| Configuration Modes | — | Passive Serial, Passive Parallel Async, Passive Parallel Sync |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |