EP20K400GI655-1 vs EP20K400GC655-3 Vergleich
Detaillierter Direktvergleich von EP20K400GI655-1 von Altera und EP20K400GC655-3 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP20K400GC655-3 - 400K Gate APEX-20KC FPGA 655-BCPGA | Intel
EP20K400GC655-3 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP20K400GI655-1 | EP20K400GC655-3 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $195,00 | $310,00 |
| Family | APEX 20K | APEX 20K |
| Device Series | EP20K400 | — |
| Technology | CMOS, SRAM-based | — |
| Logic Elements | 16640 | 16640 |
| Typical Gates | 400000 | — |
| Maximum User I/O | 502 | — |
| Dedicated Inputs | 4 | — |
| Total Terminals | 655 | — |
| Propagation Delay | 2.5 ns | — |
| Package Type | Ceramic Pin Grid Array (CPGA-655) | — |
| JESD-30 Package Code | S-CPGA-P655 | — |
| Betriebstemperatur | -40C to +85C (Industrial) | -40C to +85C (industrial) |
| Moisture Sensitivity Level | MSL 1 | — |
| Peak Reflow Temperature | 220 C | — |
| Programmability | In-system, JTAG boundary-scan (IEEE 1149.1) | — |
| Process Node | 0.18 micrometer CMOS | — |
| RoHS-Status | Compliant | [DATA_NEEDED: rohs status] |
| Series | — | APEX-20KC |
| Manufacturer | — | Intel (formerly Altera) |
| Total RAM Bits | — | 212992 |
| Number of Gates | — | 400000 |
| Supply Voltage - Core | — | 1.71 V to 1.89 V (1.8 V nominal) |
| I/O Voltage Tolerance | — | MultiVolt I/O: 1.8 V / 2.5 V / 3.3 V / 5 V |
| Maximum Frequency | — | 167 MHz (per FPGAkey) |
| Process Technology | — | 0.22 um CMOS |
| Gehäuse / Bauform | — | 655-BCPGA |
| Supplier Device Package | — | 655-CPGA (62.48 x 62.48 mm) |
| Speed Grade | — | -3 (slowest grade in family) |
| Propagation Delay (tPD) | — | 3.6 ns (per Microchip USA listing) |
| JTAG Support | — | IEEE 1149.1 Boundary-Scan |
| Configuration Modes | — | Passive Serial, Passive Parallel Sync/Async, Active Serial |