EP20K400GI655-1V vs EP20K400GC655-3V Vergleich
Detaillierter Direktvergleich von EP20K400GI655-1V von Intel und EP20K400GC655-3V von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP20K400GI655-1V - APEX 20K 400K Gate FPGA, 655-pin CBGA | Intel
EP20K400GI655-1V ⚠ Letzte Bestellmöglichkeit
Spezifikationsvergleich
| Parameter | EP20K400GI655-1V | EP20K400GC655-3V |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $155,00 | $160,00 |
| Family | APEX 20K | APEX 20KC (Apex 20KE Device Family, 1.8 V, LVDS) |
| Typical Gates | 400,000 | — |
| Logic Elements | 16,640 | 16640 |
| Maximum User I/O | 502 | — |
| Dedicated Inputs | 4 | — |
| Package Type | CBGA-655 (Ceramic Ball Grid Array) | — |
| Package Code (JESD-30) | S-CPGA-P655 | — |
| Package Equivalence Code | SPGA655, 47x47 | SPGA655, 47x47 |
| Process Technology | CMOS | CMOS |
| Propagation Delay | 2.5 ns | 3.6 ns |
| Core Supply Voltage | 2.5 V | 1.71 V to 1.89 V (1.8 V nominal) |
| I/O Supply Voltage | 2.5 V / 3.3 V | — |
| Configuration | In-system programmable via JTAG | SRAM-based (requires EPC configuration device) |
| Boundary Scan | IEEE 1149.1 JTAG | — |
| Betriebstemperatur | [DATA_NEEDED: industrial vs military grade] | [DATA_NEEDED: commercial / industrial / military grade] |
| MSL-Level | 1 | — |
| Package Body Material | Ceramic | — |
| RoHS-Status | [DATA_NEEDED] | [DATA_NEEDED: RoHS compliance flag - BCPGA package often non-RoHS] |
| Series | — | APEX-20KC |
| Manufacturer | — | Altera (now Intel) |
| Total RAM Bits | — | 212992 |
| Typical Gate Count | — | 400000 |
| Number of User I/O | — | 496 |
| Maximale Taktfrequenz | — | 714.2 MHz |
| Speed Grade | — | -3V (commercial temperature, Vcc 1.8 V) |
| Gehäuse | — | 655-BCPGA (62.48 mm x 62.48 mm) |
| Montageart | — | Through Hole (CPGA) |
| Peak Reflow Temperature | — | 220 C |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |