EP20K400GI655-1X vs EP20K400GC655-3X Vergleich
Detaillierter Direktvergleich von EP20K400GI655-1X von Altera und EP20K400GC655-3X von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP20K400GI655-1X - 400K Gate APEX 20K FPGA, 16640 Logic Elements, 655-Pin CPGA | Altera (Intel)
EP20K400GI655-1X ObsoleteSpezifikationsvergleich
| Parameter | EP20K400GI655-1X | EP20K400GC655-3X |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $160,00 | $65,00 |
| Family | APEX 20K | APEX 20K (MultiCore architecture, LUT + product-term + embedded memory) |
| Device | EP20K400 | — |
| Logic Elements | 16640 | — |
| Number of Terminals | 655 | — |
| User I/O Lines | 502 | — |
| Dedicated Inputs | 4 | — |
| Package Type | Ceramic Pin Grid Array (CPGA) | — |
| Package Code (JESD-30) | S-CPGA-P655 | — |
| Package Equivalence Code | SPGA655,47X47 | — |
| Package Body Material | CERAMIC (metal-sealed co-fired) | — |
| Speed Grade | -1 | -3 (fastest) |
| Propagation Delay | 2.5 ns (typical for -1 grade) | — |
| Process Technology | CMOS, SRAM-based configuration | 0.22 µm CMOS |
| Feuchtigkeitsempfindlichkeitsgrad (MSL) | 1 | — |
| Peak Reflow Temperature | 220 C | — |
| Betriebstemperatur | -40 C to +85 C (industrial) | [DATA_NEEDED: operating temperature range] |
| Montageart | Through-Hole (PGA) | Through-Hole (CPGA, ceramic) |
| RoHS-Status | Compliant | [DATA_NEEDED: RoHS status - ceramic CPGA historically non-RoHS] |
| Series | — | APEX-20KC |
| Manufacturer | — | Altera (now Intel FPGA) |
| Logic Elements / Cells | — | 16,640 |
| System Gates | — | 400,000 |
| Total RAM Bits | — | 212,992 bits |
| Maximum Internal Frequency | — | 167 MHz (speed grade -3) |
| Core Supply Voltage (VCCINT) | — | 1.71 V to 1.89 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V (LVDS support per APEX 20KE datasheet) |
| Gehäuse / Bauform | — | 655-BCPGA (CPGA655, 62.48 x 62.48 mm) |
| Suffix Code | — | -X (extended / ceramic CPGA variant) |
| I/O Count | — | [DATA_NEEDED: max user I/O] |
| JTAG / Boundary Scan | — | IEEE 1149.1 (per APEX 20K family) |