EP20K600CF672C6 vs EP20K600CF672C-7 Vergleich
Detaillierter Direktvergleich von EP20K600CF672C6 von Altera und EP20K600CF672C-7 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP20K600CF672C6 | EP20K600CF672C-7 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $480,00 | $1.620,00 |
| Family | APEX 20KC | — |
| Typical Gate Count | 600,000 gates | — |
| Logic Elements (LEs) | 24,320 | — |
| Embedded System Blocks (ESBs) | 160 (each 2,048 bits) | — |
| Maximum Embedded RAM | 311,296 bits (311 kbit) | — |
| Maximum User I/O Pins | 508 | — |
| Gehäuse | 672-ball FineLine BGA (CF672) | — |
| Package Body Size | 27 mm × 27 mm | — |
| Speed Grade | -6 (C6) | -7 |
| Betriebstemperatur | 0 °C to +85 °C (commercial) | 0 °C to 85 °C (Commercial) |
| Core Voltage | 1.8 V | — |
| I/O Standards Supported | LVCMOS, LVTTL, HSTL, SSTL, GTL+ | — |
| Embedded PLLs | 4 | — |
| Process Technology | 0.18 µm CMOS, 6 metal layers | 0.18 µm all-layer copper-metal (APEX 20KC) |
| Configuration Method | SRAM-based, JTAG, EPC16/EPC2 | — |
| RoHS-Status | Non-RoHS (legacy process) | — |
| Device Family | — | APEX 20KC |
| Typical Gates | — | 600,000 |
| Logic Elements | — | 24,576 |
| Maximum User I/O | — | 508 |
| Embedded Memory (ESB) | — | 311 kbits |
| Number of Terminals | — | 672 |
| Package Type | — | 672-BBGA, FCBGA |
| Package Dimensions | — | 45 x 45 mm |
| Ball Pitch | — | 1.27 mm |
| Propagation Delay | — | 1.48 ns |
| Configuration Interface | — | EPC (Enhanced Configuration) device family |
| Montageart | — | Surface Mount |
| Lead-Free / RoHS | — | [DATA_NEEDED: lead-free/RoHS status not stated in verified web data] |