EP20K600CF672C7ES vs EP20K600CF672C9 Vergleich
Detaillierter Direktvergleich von EP20K600CF672C7ES von Altera und EP20K600CF672C9 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP20K600CF672C7ES - APEX 20KC FPGA 600K Gates 672-FBGA | Altera
EP20K600CF672C7ES ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP20K600CF672C7ES | EP20K600CF672C9 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $360,00 | $171,00 |
| Series | APEX 20KC | — |
| Family | APEX 20K | — |
| Logic Elements / Cells | 24320 | — |
| System Gates | 600000 | — |
| Maximum User I/O | 504 | 488 pins |
| Maximum Input Lines | 508 | — |
| Number of Macrocells | 504 | — |
| Maximum Operating Frequency | 375.94 MHz (per FPGAkey listing) | — |
| Propagation Delay | 1.6 ns | 1.48 ns |
| Internal Reference Clock | 1666.6 MHz | — |
| Process Technology | 0.15 µm CMOS | 0.15 µm all-layer copper-metal |
| Core Supply Voltage (VCCINT) | 1.8 V | — |
| Package Type | FC-FBGA | 672-pin FC-FBGA |
| Pin / Ball Count | 672 | — |
| Grade Suffix | ES (engineering sample / extended screening) | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature grade] | 0 °C to +85 °C (commercial) |
| Montageart | Surface Mount (BGA) | — |
| MSL-Level | [DATA_NEEDED: MSL rating] | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Configuration Memory | SRAM-based (volatile) | — |
| Device Family | — | APEX 20KC |
| Typical Gate Count | — | 600,000 gates |
| Logic Elements (LEs) | — | 24,320 |
| Embedded Memory (EAB) | — | 311 Kbits |
| Maximum Internal Frequency | — | 250 MHz |
| Core Voltage | — | 1.8 V |
| Package Dimensions | — | 45 x 45 mm, 1.27 mm pitch |
| Total Pin Count | — | 652 balls |
| Configuration Interface | — | IEEE 1149.1 JTAG / passive serial / EPC configuration |