EP20K600CF672C7N vs EP20K600CF672C-7ES Vergleich

Detaillierter Direktvergleich von EP20K600CF672C7N von Altera und EP20K600CF672C-7ES von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP20K600CF672C7N EP20K600CF672C-7ES
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $108,00 $2.050,00
Device Family APEX 20KC —
Maximum System Gates 1,052,000 1,560,000 (typical 600K application gates)
Typical Gates 600,000 —
Logic Elements / Cells 24,320 —
Maximum User I/O Pins 488 —
Total Package Pins 652 —
Gehäuse FC-FBGA (BGA-652) 45 x 45 mm, 1.27 mm pitch 672-ball FCBGA (FineLine BGA), 45 x 45 mm, 1.27 mm pitch
Core Voltage 1.8 V 1.8 V (typical APEX 20KC, exact value per datasheet)
Maximum Operating Frequency 375.94 MHz —
Propagation Delay 1.48 ns 1.48 ns to 1.6 ns
Process Technology 0.15 µm all-layer copper-metal CMOS 0.15 micron all-layer copper CMOS
Architecture MultiCore (LUT + Embedded System Memory) —
Betriebstemperatur 0 °C to +85 °C (Commercial) 0 C to 85 C (Commercial)
Speed Grade C7 -7
Seated Height 3.50 mm —
Montageart Surface Mount (BGA) —
RoHS-Status unknown —
Family — APEX 20KC
Device Type — Field Programmable Gate Array (FPGA)
Typical Logic Elements — 24,320 (per APEX 20KC 600K family)
Maximum User I/O — 488
Total I/O Lines — 504 (per Microchip USA listing)
Total Inputs — 508
Embedded System Blocks (ESBs) — 248
Embedded RAM — 248 Kbits (dual-port)
PLLs — 4
Maximale Taktfrequenz — 1666.6 MHz
Configuration Mode — EPC serial / JTAG IEEE 1149.1
Compliance — RoHS status unknown (verify with manufacturer datasheet)

Datenblätter & Ressourcen

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