EP20K600CF672C9 vs EP20K600CF672I9 Vergleich

Detaillierter Direktvergleich von EP20K600CF672C9 von Intel und EP20K600CF672I9 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP20K600CF672C9 EP20K600CF672I9
Marke Intel Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus NRND Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $171,00 $152,00
Device Family APEX 20KC —
Typical Gate Count 600,000 gates —
Logic Elements (LEs) 24,320 —
Maximum User I/O 488 pins —
Embedded Memory (EAB) 311 Kbits —
Propagation Delay 1.48 ns —
Maximum Internal Frequency 250 MHz —
Core Voltage 1.8 V 1.8 V
Process Technology 0.15 µm all-layer copper-metal 0.15 µm CMOS
Package Type 672-pin FC-FBGA —
Package Dimensions 45 x 45 mm, 1.27 mm pitch —
Total Pin Count 652 balls —
Betriebstemperatur 0 °C to +85 °C (commercial) —
Configuration Interface IEEE 1149.1 JTAG / passive serial / EPC configuration —
RoHS-Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Family — APEX 20KC
Logic Elements / Cells — 24,320
System Gates — 600,000
Maximum Operating Frequency — 250 MHz
Gehäuse — 672-pin FC-FBGA
Montageart — Surface Mount (BGA)
Temperature Grade — Industrial (-40°C to +85°C)
Speed Grade — 9 (fastest bin)
User I/O Pins — 311 (max)
Embedded Array Blocks (EABs) — [DATA_NEEDED: EAB count]
Embedded Memory — [DATA_NEEDED: total RAM bits]
PLLs — Up to 4
I/O Standards Supported — LVTTL, LVCMOS, PCI, LVDS
Configuration Mode — Passive Serial / JTAG
Maximum Seated Height — 2.1 mm
MSL-Level — [DATA_NEEDED: MSL level]
Lead-Free — [DATA_NEEDED: lead-free]

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