EP20K600CF672I7N vs EP20K600CF672C7N Vergleich
Detaillierter Direktvergleich von EP20K600CF672I7N von Intel und EP20K600CF672C7N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP20K600CF672I7N | EP20K600CF672C7N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $232,00 | $108,00 |
| Family | APEX 20KC | — |
| Technology | 0.15 µm CMOS | — |
| Maximum System Gates | 600,000 | 1,052,000 |
| Logic Elements | 24,320 | — |
| Maximum User I/O Pins | 508 | 488 |
| Maximum Internal Frequency | 376 MHz | — |
| Embedded System Blocks (ESBs) | 160 | — |
| Total Embedded RAM (max) | 311,296 bits | — |
| Core Voltage (VCCINT) | 1.8 V | — |
| I/O Voltage (VCCIO) | 2.5 V / 3.3 V (MultiVolt, bank-dependent) | — |
| Gehäuse | 672-ball FineLine BGA (FC-FBGA) | FC-FBGA (BGA-652) 45 x 45 mm, 1.27 mm pitch |
| Ball Pitch | 1.0 mm | — |
| Package Body Size | 27 mm × 27 mm | — |
| Speed Grade | I7 (-40 °C to +100 °C industrial) | C7 |
| Propagation Delay (typical) | 1.6 ns | — |
| Configuration Method | JTAG (IEEE 1149.1) + EPC configuration device | — |
| Lead-Free Finish (N suffix) | Yes | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | unknown |
| Device Family | — | APEX 20KC |
| Typical Gates | — | 600,000 |
| Logic Elements / Cells | — | 24,320 |
| Total Package Pins | — | 652 |
| Core Voltage | — | 1.8 V |
| Maximum Operating Frequency | — | 375.94 MHz |
| Propagation Delay | — | 1.48 ns |
| Process Technology | — | 0.15 µm all-layer copper-metal CMOS |
| Architecture | — | MultiCore (LUT + Embedded System Memory) |
| Betriebstemperatur | — | 0 °C to +85 °C (Commercial) |
| Seated Height | — | 3.50 mm |
| Montageart | — | Surface Mount (BGA) |