EP20K600CF672I7N vs EP20K600CF672I7 Vergleich
Detaillierter Direktvergleich von EP20K600CF672I7N von Intel und EP20K600CF672I7 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP20K600CF672I7N | EP20K600CF672I7 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $232,00 | $220,00 |
| Family | APEX 20KC | APEX 20KC |
| Technology | 0.15 µm CMOS | — |
| Maximum System Gates | 600,000 | — |
| Logic Elements | 24,320 | — |
| Maximum User I/O Pins | 508 | — |
| Maximum Internal Frequency | 376 MHz | 375.94 MHz |
| Embedded System Blocks (ESBs) | 160 | — |
| Total Embedded RAM (max) | 311,296 bits | — |
| Core Voltage (VCCINT) | 1.8 V | — |
| I/O Voltage (VCCIO) | 2.5 V / 3.3 V (MultiVolt, bank-dependent) | — |
| Gehäuse | 672-ball FineLine BGA (FC-FBGA) | 672-ball FineLine BGA (FC-FBGA, 27×27 mm) |
| Ball Pitch | 1.0 mm | 1.00 mm |
| Package Body Size | 27 mm × 27 mm | — |
| Speed Grade | I7 (-40 °C to +100 °C industrial) | -7 |
| Propagation Delay (typical) | 1.6 ns | — |
| Configuration Method | JTAG (IEEE 1149.1) + EPC configuration device | — |
| Lead-Free Finish (N suffix) | Yes | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Maximum Logic Elements | — | 24,320 cells |
| System Gates | — | 600,000 |
| Maximum User I/O | — | 508 |
| Process Technology | — | 0.15 µm CMOS |
| Core Supply Voltage (VCCINT) | — | 1.8 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V (LVTTL/LVCMOS compatible) |
| Betriebstemperatur | — | -40 °C to +100 °C (industrial, I-suffix) |
| Embedded System Blocks | — | Yes (dual-port RAM / CAM) |
| Configuration Interface | — | IEEE 1149.1 JTAG, passive serial, fast passive parallel |
| Montageart | — | Surface Mount (BGA) |