EP20K60EFC144-2 vs EP20K30EFC144-1N Vergleich
Detaillierter Direktvergleich von EP20K60EFC144-2 von Altera und EP20K30EFC144-1N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP20K60EFC144-2 | EP20K30EFC144-1N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $12,75 | $125,00 |
| Series | APEX-20K | APEX-20KE |
| Family | APEX-20KE (Enhanced, 1.8 V core) | — |
| Typical Gates | 60,000 | — |
| Logic Elements | 2,560 | 1,200 |
| Total RAM Bits | 32,768 | — |
| User I/O | 92 to 93 | — |
| Core Supply Voltage | 1.71 V to 1.89 V | — |
| Internal Frequency (max) | 160 MHz | 160 MHz |
| Propagation Delay | 1.72 ns | 1.68 ns |
| Process Technology | 0.18 µm CMOS | — |
| Gehäuse | 144-LQFP (also referenced as 144-FBGA 13x13 in some sources) | — |
| Betriebstemperatur | 0 °C to +85 °C (commercial) | 0 °C to 85 °C (commercial, N suffix) |
| Montageart | Surface Mount | Surface Mount |
| JTAG Support | IEEE 1149.1 boundary scan | — |
| I/O Standards | LVTTL, LVCMOS, PCI, GTL+ | — |
| Configuration Method | Serial/Parallel passive, JTAG, EPC companion | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | Unknown - not stated in verified sources |
| Device Family | — | APEX-20K MultiCore (LUT + Product-Term + ESB) |
| Gates | — | 30,000 |
| Embedded SRAM Bits | — | 24,576 |
| User I/Os | — | 93 (per Mouser/Kynix listing); 408 (per alternate datasheet listing - see note) |
| Package Type | — | 144-pin FineLine BGA (FBGA) |
| Logic Family | — | CMOS |
| Core Technology | — | 0.22 µm CMOS, SRAM-based configuration |
| Supply Voltage (Core) | — | 1.71 V to 1.89 V (1.8 V nominal) |
| Configuration Interface | — | IEEE 1149.1 JTAG + serial configuration (external EPCx required) |