EP20K60EFC144-2 vs EP20K30EFC144-2X Vergleich

Detaillierter Direktvergleich von EP20K60EFC144-2 von Altera und EP20K30EFC144-2X von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Altera
EP20K30EFC144-2X EP20K30EFC144-2X - 30K Gate APEX 20K FPGA | Altera

EP20K30EFC144-2X - 30K Gate APEX 20K FPGA | Altera

EP20K30EFC144-2X Obsolete

Spezifikationsvergleich

Parameter EP20K60EFC144-2 EP20K30EFC144-2X
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $12,75 $58,50
Series APEX-20K —
Family APEX-20KE (Enhanced, 1.8 V core) —
Typical Gates 60,000 30,000 gates
Logic Elements 2,560 —
Total RAM Bits 32,768 —
User I/O 92 to 93 —
Core Supply Voltage 1.71 V to 1.89 V 1.8 V
Internal Frequency (max) 160 MHz —
Propagation Delay 1.72 ns —
Process Technology 0.18 µm CMOS 0.22 um
Gehäuse 144-LQFP (also referenced as 144-FBGA 13x13 in some sources) —
Betriebstemperatur 0 °C to +85 °C (commercial) —
Montageart Surface Mount Surface Mount
JTAG Support IEEE 1149.1 boundary scan —
I/O Standards LVTTL, LVCMOS, PCI, GTL+ —
Configuration Method Serial/Parallel passive, JTAG, EPC companion —
RoHS-Status [DATA_NEEDED: RoHS status] unknown
Device Family — Altera APEX 20K
Device Type — Loadable programmable logic device (FPGA/CPLD hybrid)
Number of Logic Elements / Cells — 1,200 cells (third-party parametric listing)
Number of Macrocells — 192
Number of User I/O — 93
Number of Terminals — 144
Terminal Form — Ball
Package Code — LBGA / 144-FBGA
Package Shape — Square
Speed Grade — -2X
Betriebstemperaturbereich — [DATA_NEEDED: exact operating temperature range]
Embedded RAM Bits — [DATA_NEEDED: embedded memory size]
Supported I/O Standards — [DATA_NEEDED: supported I/O standards]
Configuration Schemes — [DATA_NEEDED: supported configuration schemes]

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