EP2A15F672C9 vs EP2A15F672C7 Vergleich

Detaillierter Direktvergleich von EP2A15F672C9 von Altera und EP2A15F672C7 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP2A15F672C9 EP2A15F672C7
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $175,00 $98,00
Logic Family APEX II (CMOS) —
Usable Gates 600 K —
Logic Elements 16640 —
Macrocells 1664 —
Maximum User I/Os 492 —
Gehäuse 672-ball FC-FBGA (27 x 27 mm, 1 mm pitch, FineLine) 672-ball FineLine BGA (FCBGA)
Process Technology 0.15 µm all-layer copper (up to 8 metal layers) 0.15 µm all-layer copper, up to 8 metal layers
Core Supply Voltage 1.5 V —
I/O Supply Voltage 3.3 V —
Maximum Internal Frequency 379 MHz —
Propagation Delay 1.94 ns —
High-Speed I/O Support True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps —
Embedded Memory ESB dual-port RAM / FIFO —
Betriebstemperatur 0 °C to 85 °C (commercial) Commercial (0°C to +85°C)
Configuration Interface Passive serial / Active serial / JTAG (IEEE 1149.1) —
PLLs On-chip PLLs for clock synthesis and deskew —
Compliance RoHS - [DATA_NEEDED: status not in verified data]; IEEE 1149.1 boundary scan —
Series — APEX II (EP2A15)
Family — APEX II FPGA
Logic Elements (LE) — 16,640
Total System Gates — 425,984
Maximum User I/O — 492
Embedded Memory Bits — 425,984
Number of Macrocells / Logic Units — 16,640
Propagation Delay (tPD) — 1.69 ns
Core Voltage — 1.5 V
High-Speed I/O Standard — True-LVDS, LVPECL, PCML, HyperTransport
True-LVDS Data Rate — 1 Gbps
Package Dimensions — 27 mm × 27 mm, 1.0 mm pitch
Montageart — Surface Mount
Speed Grade — C7
RoHS-Status — [DATA_NEEDED: RoHS status]

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