EP2A25F672C7 vs EP2A25F672I8 Vergleich

Detaillierter Direktvergleich von EP2A25F672C7 von Altera und EP2A25F672I8 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP2A25F672C7 EP2A25F672I8
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus NRND Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $118,00 $125,00
Product Family APEX II —
Logic Elements 25,000 —
Maximum System Gates 1,650,000 —
Maximum RAM Bits 422,976 —
User I/O Count 492 —
Gehäuse 672-ball FCBGA (FineLine BGA) 672-ball FC-FBGA (FineLine BGA), 27 × 27 mm, 1 mm pitch
Process Technology 0.15-um all-layer copper, up to 8 metal layers 0.15 µm CMOS, up to 8 metal layers
Supply Voltage (Core) 1.5 V —
LVDS Data Rate 1 Gbps per channel (True-LVDS) —
I/O Standards Supported LVDS, LVPECL, PCML, HyperTransport LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, GTL+, PCI
Betriebstemperatur 0C to +85C (Commercial) –40 °C to +85 °C (industrial, 'I' grade)
Speed Grade -7 I8 (industrial, 8-speed-grade per APEX II ordering scheme)
Configuration Mode Passive Serial, Passive Parallel, JTAG —
RoHS-Status [DATA_NEEDED: RoHS status] unknown
Embedded System Blocks (ESB) Yes - RAM, ROM, CAM, multiplier support —
Family — APEX II
Logic Elements / Cells — 24,320
Equivalent Gates — 900,000
Embedded Memory (RAM bits) — 622,592
User I/Os — 492
Number of PLLs — 4
Core Supply Voltage — 1.5 V
Propagation Delay — 1.69 ns (typical)
Internal Performance — 333 MHz (per legacy datasheet)
LVDS / High-Speed I/O — Yes, up to 1 Gbps
Montageart — Surface Mount (BGA)
JTAG / Boundary Scan — IEEE 1149.1 compliant
Lead-Free Status — unknown

Datenblätter & Ressourcen

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