EP2A25F672C9N vs EP2A25F672I-7 Vergleich
Detaillierter Direktvergleich von EP2A25F672C9N von Intel und EP2A25F672I-7 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP2A25F672C9N | EP2A25F672I-7 |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $195,00 | $171,00 |
| Family | APEX II | APEX II |
| Logic Elements / Cells | 24320 | — |
| System Gates | Approx. 900000 | 900K (approximately) |
| Maximum User I/O | 492 | — |
| Operating Frequency | 236 MHz | — |
| Core Supply Voltage (VCCINT) | 1.425 V to 1.575 V (nominal 1.5 V) | — |
| Process Technology | 0.15 µm all-layer copper, up to 8 metal layers | 0.15 um |
| Gehäuse | 672-ball FineLine BGA (F672), 27 × 27 mm, 1.00 mm pitch | 672-pin FC-FBGA |
| Montageart | Surface Mount (BGA) | Surface Mount (Flip-Chip BGA) |
| Seated Height (max) | 2.100 mm | — |
| Propagation Delay | 2.23 ns | — |
| Logic Family | CMOS | — |
| Betriebstemperatur | 0 °C to +85 °C (commercial, C9 grade) | -40C to +85C (Industrial) |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+, SSTL-2/3, LVDS, LVPECL, PCML, HyperTransport | — |
| LVDS Data Rate | Up to 1 Gbps (True-LVDS) | — |
| Configuration Interface | Serial / Parallel PROM, JTAG, passive parallel (enhanced) | — |
| Embedded Memory | Enhanced System Blocks (ESBs) for dual-port RAM | ESBs (Embedded System Blocks) |
| Design Software | Quartus II (v5.1 or later) | — |
| RoHS-Status | Compliant (per distributor listings) | [DATA_NEEDED: rohs status] |
| Manufacturer | — | Intel (formerly Altera) |
| Device Type | — | FPGA (Field-Programmable Gate Array) |
| Logic Cells / Elements | — | 24,320 |
| Maximum Operating Frequency | — | 500 MHz |
| Core Voltage | — | 1.5 V |
| Speed Grade | — | -7 |
| Temperature Grade | — | Industrial (I) |
| Configuration Method | — | JTAG, Passive Serial, Active Serial |
| JTAG Support | — | IEEE 1149.1 Boundary Scan |
| MSL-Level | — | [DATA_NEEDED: MSL level] |