EP2A25F672I-7 vs EP2A25F672C8 Vergleich
Detaillierter Direktvergleich von EP2A25F672I-7 von Intel und EP2A25F672C8 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP2A25F672I-7 | EP2A25F672C8 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $171,00 | $951,18 |
| Family | APEX II | APEX II (EP2A25) |
| Manufacturer | Intel (formerly Altera) | — |
| Device Type | FPGA (Field-Programmable Gate Array) | — |
| System Gates | 900K (approximately) | — |
| Logic Cells / Elements | 24,320 | — |
| Maximum Operating Frequency | 500 MHz | — |
| Process Technology | 0.15 um | 0.15 microm CMOS, 8-layer copper interconnect |
| Core Voltage | 1.5 V | — |
| Gehäuse | 672-pin FC-FBGA | 672-FBGA (FineLine BGA, 27x27 mm, 1.0 mm pitch) |
| Montageart | Surface Mount (Flip-Chip BGA) | Surface Mount |
| Speed Grade | -7 | C8 |
| Betriebstemperatur | -40C to +85C (Industrial) | 0 C to 85 C (commercial) |
| Temperature Grade | Industrial (I) | — |
| Configuration Method | JTAG, Passive Serial, Active Serial | — |
| JTAG Support | IEEE 1149.1 Boundary Scan | — |
| RoHS-Status | [DATA_NEEDED: rohs status] | Non-compliant (legacy product) |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| Embedded Memory | ESBs (Embedded System Blocks) | ESB blocks (dual-port RAM, FIFO, CAM, ROM) |
| Logic Elements | — | 25,000 (typical gates) |
| Maximum System Gates | — | 40,960 |
| Macrocells / Embedded Logic | — | 2,432 macros |
| User I/O Count | — | 492 |
| Propagation Delay (tpd) | — | 1.69 ns |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI-X, GTL+, SSTL-2/3, HSTL, LVDS, LVPECL |
| LVDS Data Rate | — | 1 Gbps |
| PLL Count | — | 4 |
| I/O Banks | — | 16 |