EP2A25F672I-7 vs EP2A25F672C9 Vergleich
Detaillierter Direktvergleich von EP2A25F672I-7 von Intel und EP2A25F672C9 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP2A25F672I-7 | EP2A25F672C9 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $171,00 | $700,00 |
| Family | APEX II | APEX II |
| Manufacturer | Intel (formerly Altera) | — |
| Device Type | FPGA (Field-Programmable Gate Array) | — |
| System Gates | 900K (approximately) | — |
| Logic Cells / Elements | 24,320 | — |
| Maximum Operating Frequency | 500 MHz | — |
| Process Technology | 0.15 um | 0.15 µm all-layer copper, up to 8 metal layers |
| Core Voltage | 1.5 V | — |
| Gehäuse | 672-pin FC-FBGA | 672-ball FCBGA (FineLine BGA) |
| Montageart | Surface Mount (Flip-Chip BGA) | Surface Mount |
| Speed Grade | -7 | — |
| Betriebstemperatur | -40C to +85C (Industrial) | 0°C to 85°C (Commercial) |
| Temperature Grade | Industrial (I) | — |
| Configuration Method | JTAG, Passive Serial, Active Serial | — |
| JTAG Support | IEEE 1149.1 Boundary Scan | — |
| RoHS-Status | [DATA_NEEDED: rohs status] | [DATA_NEEDED] |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| Embedded Memory | ESBs (Embedded System Blocks) | ESBs for dual-port RAM, ROM, FIFO |
| Logic Elements (LE) | — | Approximately 25,000 |
| Macro Cells | — | 2432 |
| User I/O | — | 492 |
| Package Dimensions | — | 27 mm x 27 mm |
| Ball Pitch | — | 1.0 mm |
| Logic Family | — | CMOS |
| Propagation Delay | — | 1.69 ns |
| Versorgungsspannung | — | [DATA_NEEDED: core VCC voltage] |
| I/O Standards | — | LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL (multi-voltage 1.5/1.8/2.5/3.3 V) |
| Configuration | — | Passive Serial, Passive Parallel Synchronous, JTAG |