EP2A25F672I-9 vs EP2A25F672C7 Vergleich

Detaillierter Direktvergleich von EP2A25F672I-9 von Intel und EP2A25F672C7 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP2A25F672I-9 EP2A25F672C7
Marke Intel Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete NRND
Lagerstatus In Stock In Stock
Stückpreis (USD) $195,00 $118,00
Family APEX II —
Logic Elements (typical) 25,000 —
Maximum System Gates [DATA_NEEDED: maximum system gates] 1,650,000
Embedded System Blocks (ESB) Memory 1,125 Kbits —
Maximum User I/O Pins [DATA_NEEDED: maximum user I/O pins] —
Number of PLLs 4 —
Process Technology 0.18 µm CMOS 0.15-um all-layer copper, up to 8 metal layers
Core Voltage 1.5 V / 1.8 V (speed-grade dependent) —
Operating Temperature Grade Industrial (-40 °C to +100 °C junction) —
Speed Grade -9 -7
Gehäuse 672-pin FCBGA (FineLine BGA) 672-ball FCBGA (FineLine BGA)
Montageart Surface Mount (BGA) —
Feuchtigkeitsempfindlichkeitsgrad (MSL) 3 (per Vyrian listing) —
Peak Reflow Temperature 220 °C (per Vyrian listing) —
Configuration Method JTAG / serial configuration EPROM —
Supported I/O Standards LVTTL, LVCMOS, LVDS, PCI —
RoHS-Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Legacy Status Obsolete - consult Altera / Intel FPGA archive for documentation —
Product Family — APEX II
Logic Elements — 25,000
Maximum RAM Bits — 422,976
User I/O Count — 492
Supply Voltage (Core) — 1.5 V
LVDS Data Rate — 1 Gbps per channel (True-LVDS)
I/O Standards Supported — LVDS, LVPECL, PCML, HyperTransport
Betriebstemperatur — 0C to +85C (Commercial)
Configuration Mode — Passive Serial, Passive Parallel, JTAG
Embedded System Blocks (ESB) — Yes - RAM, ROM, CAM, multiplier support

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