EP2A25F672I-9 vs EP2A25F672C9 Vergleich

Detaillierter Direktvergleich von EP2A25F672I-9 von Intel und EP2A25F672C9 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP2A25F672I-9 EP2A25F672C9
Marke Intel Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete NRND
Lagerstatus In Stock In Stock
Stückpreis (USD) $195,00 $700,00
Family APEX II APEX II
Logic Elements (typical) 25,000 —
Maximum System Gates [DATA_NEEDED: maximum system gates] —
Embedded System Blocks (ESB) Memory 1,125 Kbits —
Maximum User I/O Pins [DATA_NEEDED: maximum user I/O pins] —
Number of PLLs 4 —
Process Technology 0.18 µm CMOS 0.15 µm all-layer copper, up to 8 metal layers
Core Voltage 1.5 V / 1.8 V (speed-grade dependent) —
Operating Temperature Grade Industrial (-40 °C to +100 °C junction) —
Speed Grade -9 —
Gehäuse 672-pin FCBGA (FineLine BGA) 672-ball FCBGA (FineLine BGA)
Montageart Surface Mount (BGA) Surface Mount
Feuchtigkeitsempfindlichkeitsgrad (MSL) 3 (per Vyrian listing) —
Peak Reflow Temperature 220 °C (per Vyrian listing) —
Configuration Method JTAG / serial configuration EPROM —
Supported I/O Standards LVTTL, LVCMOS, LVDS, PCI —
RoHS-Status [DATA_NEEDED: RoHS status] [DATA_NEEDED]
Legacy Status Obsolete - consult Altera / Intel FPGA archive for documentation —
Logic Elements (LE) — Approximately 25,000
Macro Cells — 2432
User I/O — 492
Package Dimensions — 27 mm x 27 mm
Ball Pitch — 1.0 mm
Logic Family — CMOS
Propagation Delay — 1.69 ns
Betriebstemperatur — 0°C to 85°C (Commercial)
Versorgungsspannung — [DATA_NEEDED: core VCC voltage]
I/O Standards — LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL (multi-voltage 1.5/1.8/2.5/3.3 V)
Configuration — Passive Serial, Passive Parallel Synchronous, JTAG
Embedded Memory — ESBs for dual-port RAM, ROM, FIFO

Datenblätter & Ressourcen

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