EP2A25F672I9 vs EP2A25F672I8N Vergleich
Detaillierter Direktvergleich von EP2A25F672I9 von Intel und EP2A25F672I8N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP2A25F672I8N - APEX II FPGA 900K Gates 672-BGA | Intel / Altera
EP2A25F672I8N ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP2A25F672I9 | EP2A25F672I8N |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $135,00 | $198,50 |
| Family | APEX II | APEX II |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements (LEs) | 24,320 | — |
| System Gates (typical) | 900,000 | — |
| Maximum Operating Frequency | 236 MHz | — |
| Process Technology | 0.15 µm CMOS | 0.15 µm all-layer copper-metal |
| Core Voltage (VCCINT) | 1.5 V | 1.5 V |
| Gehäuse | 672-pin FC-FBGA | 672-ball FC-FBGA (FineLine BGA) |
| Pin-Anzahl | 672 | — |
| Temperature Grade | Industrial (-40 °C to +100 °C) | — |
| Speed Grade | 9 (fastest APEX II grade) | — |
| Embedded System Blocks (ESBs) | Yes (dual-port RAM/ROM) | — |
| Maximum User I/O | [DATA_NEEDED: max user I/O pin count] | — |
| Maximum Memory Bits | 422,400 bits | — |
| PLLs | 4 | — |
| Montageart | Surface Mount (flip-chip BGA) | — |
| Peak Reflow Temperature | 220 °C (per distributor listing) | — |
| Feuchtigkeitsempfindlichkeitsgrad (MSL) | 3 | — |
| RoHS-Status | Unknown (legacy 2000s part; verify lot certificate) | unknown |
| Device | — | EP2A25 |
| Logic Elements | — | 24,320 |
| Gates | — | 900,000 |
| Embedded Memory (bits) | — | 622,592 |
| User I/Os | — | 492 |
| Package Size | — | 27 x 27 mm |
| Ball Pitch | — | 1 mm |
| Metal Layers | — | Up to 8 |
| Internal Frequency (max) | — | 333 MHz |
| Propagation Delay | — | 1.69 ns |
| Betriebstemperatur | — | 0 °C to 85 °C |
| Logic Family | — | CMOS |
| I/O Standards Supported | — | True-LVDS, LVPECL, PCML, HyperTransport |
| Configuration Method | — | SRAM-based (Altera Quartus II) |
| Lead-Free | — | unknown |