EP2A40B724C8 vs EP2A40B724C7 Vergleich
Detaillierter Direktvergleich von EP2A40B724C8 von Intel und EP2A40B724C7 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP2A40B724C8 - APEX II FPGA 1.5M Gates 540 I/O 724-FCBGA
EP2A40B724C8 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP2A40B724C8 | EP2A40B724C7 |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $615,00 | $650,00 |
| Family | APEX II | APEX II |
| Device Logic Elements / Cells | 38400 | — |
| Total System Gates | ~1.5 M | 1,500,000 |
| Total RAM Bits | 655360 | — |
| Number of I/O | 540 | — |
| Number of Logic Gates | [DATA_NEEDED: exact gate count in cells vs system gates] | — |
| Core Supply Voltage | 1.5 V (1.425 V to 1.575 V) | 1.425 V to 1.575 V (typ. 1.5 V) |
| Maximum Internal Frequency | 376 MHz | 562 MHz |
| Process Technology | 0.15 µm CMOS, all-layer copper, up to 8 metal layers | 0.15 µm CMOS, up to 8 metal layers, all-layer copper |
| I/O Standards Supported | True-LVDS, LVPECL, PCML, HyperTransport (up to 1 Gbps) | LVTTL, LVCMOS, 1.5 V/1.8 V/2.5 V/3.3 V, SSTL, HSTL, PCI, LVDS, LVPECL, PCML, HyperTransport, True-LVDS (1 Gbps) |
| Gehäuse / Bauform | 724-BBGA, FCBGA (35 x 35 mm) | — |
| Supplier Device Package | 724-BGA | — |
| Betriebstemperatur | 0 °C to 85 °C (TJ) | 0 °C to +85 °C (commercial) |
| Montageart | Surface Mount | Surface Mount (BGA) |
| Shipping Media | Tray | — |
| RoHS-Status | [DATA_NEEDED: RoHS status per datasheet] | Non-compliant (lead-bearing FCBGA) |
| Feuchtigkeitsempfindlichkeitsgrad (MSL) | [DATA_NEEDED: MSL level per JEDEC J-STD-020] | — |
| Logic Elements / Cells | — | 38,400 |
| Embedded RAM Bits | — | 655,360 |
| Maximum User I/O | — | 540 |
| PLLs | — | 4 |
| Gehäuse | — | 724-ball FCBGA (FineLine BGA), 35 mm x 35 mm |
| Configuration Method | — | JTAG (IEEE 1149.1), Passive Serial, Passive Parallel, Active Serial via EPC configuration devices |
| MultiVolt I/O Support | — | 1.5 V, 1.8 V, 2.5 V, 3.3 V |
| DDR Memory Support | — | Yes (via ESB / I/O circuitry) |
| MSL-Level | — | [DATA_NEEDED: MSL level] |