EP2A40B724C9 vs EP2A40B724C7 Vergleich
Detaillierter Direktvergleich von EP2A40B724C9 von Altera und EP2A40B724C7 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP2A40B724C9 | EP2A40B724C7 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $395,38 | $650,00 |
| Series | APEX II | — |
| Logic Elements (LE) | 38,400 | — |
| Embedded RAM Bits | 655,360 (approximately 655 Kbits / 80 Kbytes) | 655,360 |
| Number of User I/O | 540 | — |
| Betriebsversorgungsspannung | 1.425 V to 1.575 V (core) | — |
| MultiVolt I/O Support | 1.5 V, 1.8 V, 2.5 V, 3.3 V | 1.5 V, 1.8 V, 2.5 V, 3.3 V |
| Gehäuse / Bauform | 724-BBGA, FCBGA (Flip-Chip BGA) | — |
| Supplier Device Package | 724-BGA (35x35 mm) | — |
| Montageart | Surface Mount | Surface Mount (BGA) |
| Betriebstemperatur | 0C to +85C | 0 °C to +85 °C (commercial) |
| Shipping Medium | Tray | — |
| MSL-Level | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL level] |
| RoHS-Status | [DATA_NEEDED: RoHS status] | Non-compliant (lead-bearing FCBGA) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Architecture | LUT-based with embedded memory blocks | — |
| Typical Core Power | [DATA_NEEDED: ICCDAT typical] | — |
| Family | — | APEX II |
| Logic Elements / Cells | — | 38,400 |
| Total System Gates | — | 1,500,000 |
| Maximum User I/O | — | 540 |
| Core Supply Voltage | — | 1.425 V to 1.575 V (typ. 1.5 V) |
| Process Technology | — | 0.15 µm CMOS, up to 8 metal layers, all-layer copper |
| Maximum Internal Frequency | — | 562 MHz |
| PLLs | — | 4 |
| Gehäuse | — | 724-ball FCBGA (FineLine BGA), 35 mm x 35 mm |
| I/O Standards Supported | — | LVTTL, LVCMOS, 1.5 V/1.8 V/2.5 V/3.3 V, SSTL, HSTL, PCI, LVDS, LVPECL, PCML, HyperTransport, True-LVDS (1 Gbps) |
| Configuration Method | — | JTAG (IEEE 1149.1), Passive Serial, Passive Parallel, Active Serial via EPC configuration devices |
| DDR Memory Support | — | Yes (via ESB / I/O circuitry) |