EP2A40F1020C8N vs EP2A40F1020I8N Vergleich
Detaillierter Direktvergleich von EP2A40F1020C8N von Intel und EP2A40F1020I8N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP2A40F1020C8N | EP2A40F1020I8N |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $125,40 |
| Product Type | Field-Programmable Gate Array (FPGA) | — |
| Device Family | APEX II | — |
| Logic Technology | CMOS | — |
| Logic Gates | 1.5 million | — |
| Logic Cells | 38,400 | — |
| Nominal Supply Voltage | 1.5 V | — |
| Supply Voltage Range | 1.425 V to 1.575 V | — |
| User I/Os | 735 | — |
| Package Terminal Count | 1,020 pins | — |
| Package Type | FC-FBGA, BGA-1020 | — |
| Package Body Size | 33 mm x 33 mm | — |
| Ball Pitch | 1 mm | — |
| Reported Operating Frequency | 376 MHz | — |
| Alternative Reported Frequency | 562 MHz | — |
| Reported Propagation Delay | 1.78 ns | — |
| Alternative Reported Propagation Delay | 1.55 ns | — |
| Fabrication Process | 0.15 µm | — |
| Maximum Reported Metal Layers | 8 layers | — |
| Betriebstemperatur | 0 °C to 85 °C | — |
| Montageart | Surface Mount | Surface Mount (BGA) |
| Terminal Form | Ball | — |
| RoHS-Status | unknown | [DATA_NEEDED: RoHS status] |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | unknown | — |
| Family | — | APEX II (EP2A40) |
| Logic Elements | — | 38,400 cells |
| System Gates | — | 1.5 M (typical) |
| Process Technology | — | 0.15 um CMOS |
| Core Voltage | — | 1.5 V |
| Maximum Internal Frequency | — | 376 MHz |
| User I/O Count | — | 735 (maximum) |
| Gehäuse | — | 1020-pin FC-FBGA (Flip-Chip Fine-pitch BGA) |
| Operating Temperature Grade | — | Industrial (-40 C to +100 C) / 'I' suffix |
| Speed Grade | — | 8 |
| Architecture | — | LUT-based with embedded system blocks (ESBs) |
| Configuration | — | SRAM-based, JTAG / passive serial / passive parallel |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Number of PLLs | — | [DATA_NEEDED: PLL count] |
| Total Embedded Memory | — | [DATA_NEEDED: embedded memory bits] |