EP2A40F1020C8N vs EP2A40F1020I9 Vergleich
Detaillierter Direktvergleich von EP2A40F1020C8N von Intel und EP2A40F1020I9 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP2A40F1020C8N | EP2A40F1020I9 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $2.105,00 |
| Product Type | Field-Programmable Gate Array (FPGA) | — |
| Device Family | APEX II | — |
| Logic Technology | CMOS | — |
| Logic Gates | 1.5 million | — |
| Logic Cells | 38,400 | 38,400 |
| Nominal Supply Voltage | 1.5 V | — |
| Supply Voltage Range | 1.425 V to 1.575 V | — |
| User I/Os | 735 | — |
| Package Terminal Count | 1,020 pins | — |
| Package Type | FC-FBGA, BGA-1020 | — |
| Package Body Size | 33 mm x 33 mm | — |
| Ball Pitch | 1 mm | — |
| Reported Operating Frequency | 376 MHz | — |
| Alternative Reported Frequency | 562 MHz | — |
| Reported Propagation Delay | 1.78 ns | — |
| Alternative Reported Propagation Delay | 1.55 ns | — |
| Fabrication Process | 0.15 µm | — |
| Maximum Reported Metal Layers | 8 layers | — |
| Betriebstemperatur | 0 °C to 85 °C | [DATA_NEEDED: junction temperature range for I9 grade] |
| Montageart | Surface Mount | Surface Mount (BGA) |
| Terminal Form | Ball | — |
| RoHS-Status | unknown | [DATA_NEEDED: confirm RoHS compliance for FC-FBGA] |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | unknown | — |
| Family | — | APEX II |
| Series | — | EP2A |
| System Gates | — | 1.5 M |
| Maximum Operating Frequency | — | 366 MHz |
| Process Technology | — | 0.15 µm |
| Core Voltage | — | 1.5 V |
| Gehäuse | — | 1020-pin FC-FBGA |
| Pin-Anzahl | — | 1020 |
| Temperature Grade | — | Industrial (I9) |
| Logic Element Type | — | 4-input LUT |
| Embedded Memory | — | ESBs (dual-port RAM / ROM / FIFO) |
| Configuration Method | — | JTAG / passive serial / passive parallel |