EP2A40F1020I9N vs EP2A40F1020C7N Vergleich
Detaillierter Direktvergleich von EP2A40F1020I9N von Intel und EP2A40F1020C7N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP2A40F1020C7N - APEX II 1.5M Gates FPGA, 735 I/O, FC-FBGA-1020 | Intel
EP2A40F1020C7N ObsoleteSpezifikationsvergleich
| Parameter | EP2A40F1020I9N | EP2A40F1020C7N |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $165,00 | $198,00 |
| Family | APEX II | APEX II |
| Device Logic Elements / Cells | 38,400 cells | — |
| System Gates | 1,500,000 (1.5 M) | 1,500,000 (1.5 M) |
| Maximum Operating Frequency | 366 MHz | — |
| Process Technology | 0.15 um CMOS, up to 8 metal layers | — |
| Core Supply Voltage | 1.5 V | 1.5 V nominal (1.425 V – 1.575 V) |
| User I/O Count | 735 bidirectional I/O | — |
| Gehäuse | 1020-pin FC-FBGA (Flip-Chip FineLine BGA) | FC-FBGA-1020, 33 × 33 mm, 1.0 mm pitch, fine-line |
| Operating Temperature Grade | Industrial (I9 suffix: -40C to +100C per Altera APEX II convention) | — |
| High-Speed I/O Standards | True-LVDS (up to 1 Gbps), LVPECL, PCML, HyperTransport | — |
| Embedded Memory | ESB-based True-Dual-Port/Single-Port RAM, ROM, CAM (bits [DATA_NEEDED: total RAM bits]) | ESB-based, 504 Kbits total |
| Clock Management | PLLs (count [DATA_NEEDED: PLL count]) | — |
| Configuration Modes | Passive Serial, Passive Parallel Asynchronous/Synchronous, JTAG | — |
| Montageart | Surface Mount (BGA) | Surface Mount |
| RoHS-Status | [DATA_NEEDED: RoHS status] | — |
| Lebenszyklusstatus | Obsolete (per distributor listings / Altera APEX II family EOL) | — |
| Technology | — | 0.15 µm all-layer copper CMOS, up to 8 metal layers |
| Logic Elements | — | 38,400 |
| Maximum Internal Performance | — | 562 MHz |
| Propagation Delay | — | 1.55 ns |
| User I/O Pins | — | 735 |
| PLLs | — | 4 |
| Clock Networks | — | 12 |
| True-LVDS Data Rate | — | 1 Gbps |
| Supported I/O Standards | — | True-LVDS, LVPECL, PCML, HyperTransport, LVTTL, LVCMOS, PCI, SSTL |
| Logic Family | — | CMOS |
| Betriebstemperatur | — | 0 °C to +85 °C (commercial, C7 grade) |
| Terminal Form | — | BGA ball (flip-chip) |