EP2A40F672C6N vs EP2A40F672C7 Vergleich
Detaillierter Direktvergleich von EP2A40F672C6N von Intel und EP2A40F672C7 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP2A40F672C6N | EP2A40F672C7 |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $165,00 | $195,00 |
| Family | APEX II | APEX II |
| Logic Elements | 40,000 | 38,400 |
| Maximum System Gates | 1,125,000 | — |
| Embedded RAM Bits | 442,368 | — |
| Embedded System Blocks (ESBs) | 160 | — |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O count] | — |
| Core Voltage | 1.5 V | 1.5 V |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+, SSTL, HSTL, 1.8V/2.5V/3.3V/5V | — |
| Gehäuse | 672-ball FineLine BGA | 672-ball FC-FBGA (FineLine BGA) |
| Betriebstemperatur | Commercial (0C to +85C) | — |
| Speed Grade | C6 (per part number suffix) | — |
| Configuration Methods | Passive Serial, Passive Parallel, JTAG | — |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | Compliant |
| Process Technology | SRAM-based, 0.18 um (per family datasheet) | 0.15 µm CMOS, all-layer copper, up to 8 metal layers |
| PLL Count | [DATA_NEEDED: PLL count] | — |
| System Gates | — | 1,500,000 |
| Macro Cells | — | 2,560 |
| Maximum User I/O | — | 492 |
| I/O Voltage Support | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| Pin-to-Pin Delay | — | 1.55 ns (C7 speed grade) |
| Maximum Internal Frequency | — | 562 MHz |
| High-Speed Interface | — | 1 Gbps True-LVDS, LVPECL, PCML, HyperTransport |
| PLLs | — | 4 |
| Package Dimensions | — | 27 x 27 mm, 1.0 mm pitch |
| Operating Temperature Grade | — | Commercial (per 'C' suffix in speed grade) |
| Lead-Free | — | Yes |