EP2A40F672C6N vs EP2A40F672C9ES Vergleich
Detaillierter Direktvergleich von EP2A40F672C6N von Intel und EP2A40F672C9ES von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP2A40F672C6N | EP2A40F672C9ES |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $165,00 | $195,00 |
| Family | APEX II | APEX II |
| Logic Elements | 40,000 | 38,400 |
| Maximum System Gates | 1,125,000 | — |
| Embedded RAM Bits | 442,368 | — |
| Embedded System Blocks (ESBs) | 160 | — |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O count] | — |
| Core Voltage | 1.5 V | 1.5 V |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+, SSTL, HSTL, 1.8V/2.5V/3.3V/5V | — |
| Gehäuse | 672-ball FineLine BGA | 672-pin FC-FBGA |
| Betriebstemperatur | Commercial (0C to +85C) | — |
| Speed Grade | C6 (per part number suffix) | -9 |
| Configuration Methods | Passive Serial, Passive Parallel, JTAG | — |
| Montageart | Surface Mount | Surface Mount (BGA) |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | unknown |
| Process Technology | SRAM-based, 0.18 um (per family datasheet) | 0.15 µm CMOS |
| PLL Count | [DATA_NEEDED: PLL count] | — |
| System Gates | — | 1,500,000 |
| Maximum User I/O | — | 492 |
| Operating Frequency (max) | — | 366 MHz |
| Configuration Modes | — | PS, PPS, PPA, JTAG, FPP |
| Embedded Memory (ESB) | — | Yes (RAM/ROM/CAM) |
| I/O Standards | — | LVTTL, LVCMOS, PCI, SSTL, HSTL, GTL+ |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |